臺灣博碩士論文加值系統

本論文第一部份是IEEE 802.11a WLAN 接收器射頻系統之設計規劃，論文第二部份是選定直接降頻式接收器架構，利用TSMC CMOS 0.18um 的製程設計5GHz差動式低雜訊放大器。
串疊式型態的低雜訊放大器在無線通訊系統上相當受到歡迎。為了得到良好的雜訊特性選用主動元件的方法是採用Thomas Lee教授所提出的方法，加入源極回授電感可以將等雜訊圓與等功率增益圓拉得很靠近，使輸入阻抗匹配更容易去達成。
本論文之差動式低雜訊放大器在5.25GHz模擬結果為：輸入返回損耗26dB、輸出返回損耗14dB、增益為13.771dB、雜訊指數為2.524dB、P1dB 為-14.541dBm、OIP3為-4.057dBm。

This thesis presents: (1) the study of RF system planning and receiver architecture for IEEE 802.11a WLAN OFDM system, and (2) development of 5GHz CMOS differential LNA RF ICs for a direct-conversion receiver. The 5GHz CMOS differential LNA uses a TSMC standard 0.18μm CMOS technology.
Cascode topologies of the low noise amplifiers are quietly popular for the wireless communication system. Selecting devices for getting good noise performances are given by the Thomas Lee’s method. Adding source feedback inductances can make noise circles and available power gain circles closer, therefore input matching can be more easily achieved.
The simulation results for the differential low noise amplifier at 5.25GHz are as follows: input and output return loss are greater than 26dB and 14dB, gain is 13.771dB, noise figure is 2.524dB, is -14.541dBm, and the OIP3 is -4.057dBm.

目 錄
中文摘要…………………………………………………………………2
英文摘要…………………………………………………………………3
目錄………………………………………………………………………4
第一章 緒論
1.1研究動機...............................................11
1.2論文組織...............................................12
第二章 接收器系統架構與低雜訊放大器的設計考量
2.1 簡介..................................................13
2.2 接收器系統架構........................................13
2.2.1 超外差式接收器..................................13
2.2.2 雙降頻式超外差接收器................................15
2.2.3直接降頻接收器.......................................16
2.3 射頻前端接收器效能參數與LNA的規格參考.................19
2.3.1 雜訊指數............................................19
2.3.2 LNA的增益及穩定度...................................20
2.3.3 LNA的線性度.........................................23
2.3.4 LNA的規格參考.......................................23
第三章 CMOS低雜訊放大器之設計
3.1 簡介..................................................24
3.2 CMOS低雜訊放大器電路架構..............................24
3.3 積體電路內部的雜訊來源................................26
3.3.1通道熱雜訊...........................................26
3.3.2分佈閘極電阻雜訊.....................................27
3.3.3感應閘極電流雜訊.....................................28
3.4 CMOS低雜訊放大器之設計(一)............................29
3.4.1 CMOS低雜訊放大器雜訊模型推導........................29
3.4.2 CMOS低雜訊放大器設計方法(一)的設計流程..............35
3.4.3 CMOS低雜訊放大器設計方法(一)的模擬結果..............42
3.5 CMOS低雜訊放大器之設計(二)............................45
3.5.1 CMOS低雜訊放大器設計方法(二)的設計流程..............45
3.5.2 CMOS低雜訊放大器設計方法(二)的模擬結果..........51
第四章 模擬結果及量測考量
4.1 簡介..................................................54
4.2 本論文之Single-End CMOS低雜訊放大器設計方法...........54
4.2.1 本論文之Single-End CMOS LNA設計流程.................55
4.3 本論文之Differential CMOS低雜訊放大器設計.............60
4.4 本論文之Differential CMOS低雜訊放大器模擬結果.........61
4.4.1比較三種不同設計方法的差異...........................67
4.5本論文之CMOS差動式低雜訊放大器量測考量.................69
第五章 結語 ..............................................74
參考文獻..................................................75

參考文獻
[1] Liang-Hui Li, RF System Planning of 802.11a WLAN Receiver and 5GHz CMOS Differential LNA/Mixer Circuit Design, Department of Electrical Engineering National Cheng Kung University, Tainan, Taiwan, R.O.C. Thesis for Master of Science June, 2002.
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[19]H. W. Chiu, and S. S. Lu, "A 2.17dB NF, 5 GHz Band Monolithic CMOS LNA with 10 mW DC Power Consumption," VLSI Circuits Digest of Technical Papers, 2002. Symposium on,13-15 pp. 226-229, June 2002
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