|
[1] Alan C. Seabaugh, Qin Zhang, “Low-Voltage Tunnel Transistors for Beyond CMOS Logic,” Proceedings of the IEEE, vol.98, no.12, pp.2095-2110, Dec. 2010
[2] K. Gopalakrishnan, P.B. Griffin, J.D. Plummer, “I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q,” Electron Devices Meeting(IEDM), 2002 IEEE International, pp.289-292, 8-11 Dec. 2002
[3] Hei Kam, D.T. Lee, R.T. Howe, Tsu-Jae King, “A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics,” Electron Devices Meeting(IEDM), 2005 IEEE International, pp.463-466, 5-5 Dec. 2005
[4] Sayeef Salahuddin, Supriyo Datta, “Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices” Nano Letters, pp.405-410, 2008
[5] Woo Young Choi, Byung-Gook Park, Jong-Duk Lee, Tsu-Jae King Liu, “Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec,” Electron Device Letters IEEE, vol.28, no.8, pp.743-745, Aug. 2007
[6] Han Zhao, Yen-Ting Chen, Yanzhen Wang, Fei Zhou, Fei Xue, Jack C. Lee, “Improving the on-current of In0.7Ga0.3As tunneling field-effect-transistors by p++/n+ tunneling junction,” Applied Physics Letters, vol.98, 2011.
[7] Krishnamohan Tejas, Donghyun Kim, Shyam Raghunathan, K. Saraswat, “Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope”, Electron Devices Meeting(IEDM), 2008 IEEE International, pp.1-3, 15-17 Dec. 2008.
[8] D.K. Mohata, R. Bijesh, Y. Zhu, M. K. Hudait, R. Southwick, Z. Chbili, D. Gundlach, J. Suehle, J. M. Fastenau, D. Loubychev, A K. Liu, T.S. Mayer, V. Narayanan, S. Datta, “Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio,” VLSI Technology (VLSIT), 2012 Symposium on , pp.53-54, 12-14 June 2012
[9] AW. Dey, B.M. Borg, B. Ganjipour, Martin Ek, Kimberly A Dick, E. Lind, P. Nilsson, C. Thelander, L.-E. Wernersson, “High current density InAsSb/GaSb tunnel field effect transistors,” Device Research Conference (DRC), 2012 70th Annual , pp.205,206, 18-20 June 2012.
[10] Guangle Zhou, Yeqing Lu, Rui Li, Qin Zhang, Qingmin Liu, T. Vasen, Haijun Zhu, Jenn-Ming Kuo, T. Kosel, M. Wistey, P. Fay, A Seabaugh, Huili Xing, “InGaAs/InP Tunnel FETs With a Subthreshold Swing of 93 mV/dec and ION/IOFF Ratio Near 106 ,” Electron Device Letters, IEEE , vol.33, no.6, pp.782,784, June 2012
[11] Guangle Zhou, R. Li, T. Vasen, M. Qi, S. Chae, Y. Lu, Q. Zhang, H. Zhu, J.-M. Kuo, T. Kosel, M. Wistey, P. Fay, A Seabaugh, Huili Xing, ”Novel gate-recessed vertical InAs/GaSb TFETs with record high ION of 180 μA/μm at VDS = 0.5 V,” IEDM Tech. Dig., pp.32.6.1-32.6.4, 10-13 Dec. 2012.
[12] T. Skotnicki, C. Fenouillet-Beranger, C. Gallon, F. Boeuf, S. Monfray, F. Payet, A. Pouydebasque, M. Szczap, A. Farcy, F. Arnaud, S. Clerc, M. Sellier, A. Cathignol, J.-P. Schoellkopf, E. Perea, R. Ferrant and H. Mingam, “Innovative materials, devices, and CMOS technologies for low-power mobile multimedia”, IEEE Transactions on Electron Devices, vol. 55, no. 1, pp.96-128, Jan. 2008.
[13] Tomohisa Mizuno, J. Okumtura, Akira Toriumi, “Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's,” IEEE Transactions on Electron Devices, vol.41, no.11, pp.2216-2221, Nov. 1994
[14] Hon-Sum Wong, Yuan Taur, “Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 um MOSFET's,” Electron Devices Meeting (IEDM), 1993 IEEE International, pp.705-708, 5-8 Dec. 1993
[15] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. Mclntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams and K. Zawadzki, “A 45 nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging”, Electron Devices Meeting (IEDM), 2007 IEEE International, pp.247-250, 2007.
[16] K. Ohmori, T. Matsuki, D. Ishikawa, T. Morooka, T. Aminaka, Y. Sugita, T. Chikyow, K. Shiraishi, Y. Nara, K. Yamada, “Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates”, Electron Devices Meeting (IEDM), 2008 IEEE International, pp.1-4, 2008.
[17] Y. X. Liu, K. Endo, S. O'uchi, T. Kamei, J. Tsukada, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, T. Matsukawa, A Ogura, M. Masahara, “On the gate-stack origin threshold voltage variability in scaled FinFETs and multi-FinFETs”, VLSI Technology (VLSIT), 2010 Symposium on, pp.101,102, 2010.
[18] U.E. Avci, R. Rios, K. Kuhn, IA Young, “Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic,” VLSI Technology (VLSIT), 2011 Symposium on, pp.124-125, 14-16 June 2011.
[19] V. Saripalli, S. Datta, V. Narayanan, J. P. Kulkarni, “Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design,” Nanoscale Architectures, 2011 IEEE/ACM International Symposium on , pp.45-52, 8-9 June 2011
[20] R. Pandey, B. Rajamohanan, Huichu Liu, V. Narayanan, S. Datta, “Electrical Noise in Heterojunction Interband Tunnel FETs,” IEEE Transactions on Electron Devices, vol.61, no.2, pp.552-560, Feb. 2014
[21] Kyoung Min Choi, Woo Young Choi, “Work-Function Variation Effects of Tunneling Field-Effect Transistors (TFETs)”, IEEE Electron Device Letters, vol.34, no.8, pp.942-944, Aug. 2013.
[22] Ming-Long Fan, V.P.-H. Hu, Yin-Nein Chen, Pin Su, Ching-Te Chuang, “Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET”, IEEE Transactions on Electron Devices, vol.60, no.6, pp.2038-2044, June 2013.
[23] Shao-Heng Chou, Ming-Long Fan, Pin Su, “Investigation and Comparison of Work Function Variation for FinFET and UTB SOI Devices Using a Voronoi Approach”, IEEE Transactions on Electron Devices, vol.60, no.4, pp.1485-1489, April 2013.
[24] Sentaurus TCAD, Manual, Sentaurus Device, 2011.
[25] M. Luisier, G. Klimeck, “Performance comparisons of tunneling field-effect transistors made of InSb, Carbon, and GaSb-InAs broken gap heterostructures”, Electron Devices Meeting (IEDM), 2009 IEEE International, pp.1-4, 7-9 Dec. 2009.
[26] Lu Liu, D. Mohata, S. Datta, “Scaling Length Theory of Double-Gate Interband Tunnel Field-Effect Transistors”, IEEE Transactions on Electron Devices, vol.59, no.4, pp.902-908, April 2012.
[27] http://www.itrs.net/
[28] K.J. Kuhn, “Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS,” Electron Devices Meeting (IEDM), 2007 IEEE International, pp.471-474, 10-12 Dec. 2007
[29] A. Asenov, “Simulation of Statistical Variability in Nano MOSFETs,” VLSI Technology (VLSIT), 2007 IEEE Symposium on, pp.86-87, 12-14 June 2007
[30] S.S. Sylvia, K.M.M. Habib, M.A. Khayer, K. Alam, M. Neupane, R.K. Lake, “Effect of Random, Discrete Source Dopant Distributions on Nanowire Tunnel FETs,” IEEE Transactions on Electron Devices, vol.61, no.6, pp.2208-2214, June 2014
[31] Nobuyuki Sano, Kazuya Matsuzawa, Mikio Mukai, Noriaki Nakayama, “On discrete random dopant modeling in drift-diffusion simulations: physical meaning of ‘atomistic’ dopants,” Microelectronics Reliability, Volume 42, Issue 2, pp. 189-199, February 2002
[32] T. Ezaki, T. Ikezawa, A Notsu, K. Tanaka, M. Hane, , “3D MOSFET simulation considering long-range Coulomb potential effects for analyzing statistical dopant-induced fluctuations associated with atomistic process simulator,” Simulation of Semiconductor Processes and Devices, International Conference on , pp.91,94, 2002
[33] L. De Michielis, L. Lattanzio, A-M. Ionescu, “Understanding the Superlinear Onset of Tunnel-FET Output Characteristic,” IEEE Electron Device Letters, vol.33, no.11, pp.1523-1525, Nov. 2012
[34] T. Matsukawa, Yongxun Liu, W. Mizubayashi, J. Tsukada, H. Yamauchi, K. Endo, Y. Ishikawa, S. O'uchi, H. Ota, S. Migita, Y. Morita, M. Masahara, “Suppressing Vt and Gm variability of FinFETs using amorphous metal gates for 14 nm and beyond,” Electron Devices Meeting (IEDM), 2012 IEEE International, pp.8.2.1-8.2.4, 10-13 Dec. 2012
|