臺灣博碩士論文加值系統

為了增加驅動電流和傳輸速度，電晶體勢必要一直微縮下去，但是隨著元件微縮至100 奈米以下，短通道效應如DIBL跟Vth variation 皆更加嚴重，使元件的微縮更加困難。傳統抑制短通道效應的方法，像高濃度的基板掺雜、超薄的閘極介電層等，在50 奈米以下皆不再能夠有效的抑制短通道效應。因此採用新的材料和新的元件結構成為能改進電流特性及解決短通道效應最根本且有效的方法，如high –κ閘極介電層、metal gate、三五族當通道材料和三閘極電晶體(Tri-gate)。其中，三閘極電晶體由於擁有和傳統VLSI CMOS相容的製程、極佳的電流傳輸特性跟抑制短通道的能力，被科技產業寄望能延續莫爾定律到通道10 nm 以下的結構。
由於元件縮小到奈米尺寸，傳統的長通道理論公式皆會出現誤差，所以探討電晶體的載子傳輸機制的理論成為重要的議題。我們的實驗團隊已經對研究載子的傳輸模型很有經驗，在這篇論文中，我們首先介紹所使用的元件結構和製程技術，並展示我們所使用元件的基礎特性和一些常見電性參數的萃取方法，像是串聯電阻，遷移率和入射速度的萃取方法，我們實驗的結果顯示，三閘極電晶體對短通道效應有較強的抵抗力，並由於全空乏(Fully-Depleted)的操作，三閘極電晶體擁有較佳的開關特性。在效能方面，三閘極電晶體也展露了較高的載子傳輸速度。之後，我們用Virtual Source Model(VSM)萃取出來的傳輸參數跟傳統的方法做了比較。在串聯電組方面，VSM考慮了隨著閘極電壓改變的電阻，跟傳統的固定串聯電阻有很大的差別，因此在萃取遷移率的數值會介在實驗量測數據和固定串聯電阻修正的中間。在速度方面，不同於保合速度模型，VSM萃取出的速度在較低的電場下，有表現出v= E的關係，但是在入射速度方面，因為兩個模型對入射速度的定義不同，所以VSM萃取的入射速度會比保合速度模型小一些。
在熟悉了VSM模型的物理意義，我們應用這個模型在Spice上建立出可以預測汲極電流變異量的Spice模型。首先，我們從實驗結果分析出會造成汲極電流變異量的原因是由Vth和gm,max的變異所導致，所以利用了Pelgrom plot計算出不同元件面積下Vth和gm,max的變異量，並代入模型中即可得到變異的Id曲線。接著，我們在多個常見的CMOS邏輯電路上做驗證，例如 CMOS反向器，NAND, NOR和latch等邏輯電路，由這些邏輯電路我們歸納出一些結論: (1)我們成功的採用 VSM 的方法，用實驗擷取出符合物理理論的傳輸參數。(2)在三閘極電晶體中，造成汲極電流變異的主因是Vth和gm,max的變異所造成。 (3)利用Vth和gm,max的Pelgrom plot建立出以VSM為基礎的Spice變異模型，並成功模擬出單一個場效電晶體實驗量測汲極電流變異量的數據。(4)將此Spice變異模型應用到簡單的邏輯電路上也可以成功預測出不同面積下的特性圖變異量。(5)由邏輯電路的變異量與場效電晶體的數目，我們歸納出當邏輯電路串接的場效電晶體越多，其特性圖的變異量就會減少，彼此場效電晶體間會互相牽制，從另一個角度看就是元件的有效面積變大，變異量變小。本文中利用傳輸模型建立的Spice變異模型，可以預測不同尺寸元件下汲極電流的變異量和邏輯電路特性圖的變異量，對於未來在研究CMOS元件邏輯電路的變異量上可提供重要的參考指標。

In order to improve the drive current, the most efficient way is scaling down the channel length. As channel length continues scaling down below 100 nm, the short channel effects, such as Vth variation and DIBL leakage, become increasingly important. To overcome these challenges, high-k gate dielectric layers, metal gate, III-V material for channel, and 3D structures are the most possible solutions. Among all these new solutions, the tri-gate MOSFET devices exhibit excellent I-V characteristics and manufacturing ability, which is believed to be able to continue Moore’s law down to 10 nm and beyond.

Because of the scaling of CMOS devices, the common theories are not enough to describe the characteristic of short channel devices. Our group has studied the transport theory for many years. In this thesis, we outlined the advance devices used in this study and demonstrated the performance of tested devices by transport model. The results show that tri-gate CMOS devices are immune to short channel effects and are superior to its planar ones. Tri-gate devices show high velocity, which results from double gate operation that boosts the mobility of tri-gate device. Furthermore, we applied Virtual Source Model (VSM) on tri-gate devices to compare the transport parameters with common methods. The VSM considers the Vg depended series resistance that is unlike the common method- Campbell’s approach. So, the effective mobility of VSM is in the middle of measured data and the mobility that corrected by constant RSD. Due to the definitions of VSM and common method- Saturation Velocity model are different, the values of injection velocity are different, too.

After understanding the physical meanings of VSM, we use this transport model to develop a Spice variation model that can predict the Id variation of various area tri-gate devices. At first, we find that the main influence of Id variation are the variation of Vth and gm,max. Therefore, we can consider the Avt and Agm, which are defined from the Pelgrom plot respectively in our Spice variation model. We demonstrate the spice model on some basic logic circuits, such as CMOS inverter, NAND, NOR and latch which is serving as the storage of SRAM. By analyzing the above experiments, we can drawn some conclusions: (1) We have successfully used VSM to extract transport parameters that are compliance with the physical theory, (2) the main influence of Id variation are cause by the variation of Vth and gm,max, (3) we successfully built a Spice variation model that can model the characteristic and Id variation of a tri-gate device, (4) the model is used to simulate the characteristics of CMOS inverter, NAND, NOR and latch, and the results show great matches, and finally, (5) from the above results, we found that the Vth or Vsw variations of circuits can be easily calculated from the device size and respective Avt of Pelgrom plot. A variation model has been developed and demonstrated on an advanced tri-gate CMOS technology that can predict the variation of devices and circuits at various areas. These studies will be helpful and valuable for the design of the advanced tri-gate CMOS devices.

Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation of This Work 2
1.3 Organization of This Thesis 4
Chapter 2 Devices Preparation and Traditional Analysis 5
2.1 Introduction of Tri-gate MOSFETs 5
2.2 Device Preparation and Experimental Setup 8
2.2.1 Device Preparation 8
2.2.2 Measuring Facility and Basic Experimental Setup 9
2.3 Traditional Analysis of Source/Drain Series Resistance 9
2.3.1 Overview of S/D Series Resistance 10
2.3.2 Campbell’s Approach 11
2.3.3 Extraction of RSD by Campbell’s Approach 12

Chapter 3 The transport theory of the Virtual source model and the comparison with the convention 22
3.1 Introduction 22
3.2 The Saturation Velocity Model 23
3.2.1 Conventional Empirical Equation 23
3.2.2 Analysis of ballistic efficiency and injection velocity of SVM 26

3.3 The Virtual Source Model 29
3.3.1 Derivation of Id equation 29
3.3.2 Extraction of transport parameters by Virtual source model 32

3.4 Comparison of the transport parameters Between VSM and the conventional methods 33
3.4.1 The S/D Series Resistance 33
3.4.2 The Effective Mobility 34
3.4.3 The Saturation velocity and Injection velocity 35

Chapter 4 The Circuit Level Variability Model of Tri-gate CMOS Devices 52
4.1 Introduction 52
4.2 The Device Transport Model 53
4.3 The Variation Model-from Device to Circuit 54
4.3.1 The variation source of drain current 54
4.3.2 Build a Spice Variation Model 55
4.3.3 Experimental Demonstrations for Device Level 57
4.4 The Circuit Variation-for Basic Logic gates 59
4.4.1 The Circuit Level of Two Devices Connections 59
4.4.2 The Circuit of More Than Two Devices Connections 61
4.5 Summary 63

Chapter 5 Summary and Conclusion 91
References 93

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