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研究生:陳冠夫
研究生(外文):Kuan-Fu Chen
論文名稱:JPEG-2000方塊編碼器核心設計
論文名稱(外文):EFFICIENT ARCHITECTURE DESIGN OF EBCOT FOR JPEG-2000
指導教授:陳良基陳良基引用關係
指導教授(外文):Liang-Gee Chen
學位類別:碩士
校院名稱:國立臺灣大學
系所名稱:電機工程學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:中文
論文頁數:89
中文關鍵詞:JPEG-2000、EBCOT、靜態影像、壓縮、架構設計、標準、JPEG
外文關鍵詞:JPEG-2000、EBCOT、Still image、compression、hardware architecture、standard、JPEG
相關次數:
  • 被引用被引用:2
  • 點閱點閱:300
  • 評分評分:
  • 下載下載:29
  • 收藏至我的研究室書目清單書目收藏:3
隨著網際網路的蓬勃發展與數位相機的廣泛使用,靜態數位影像大量的使用於傳輸與儲存媒介。JPEG-2000是一個新制訂完成的靜態影像壓縮標準,它比目前通用的JPEG標準有更高的壓縮效能,並且可以支援許多新且實用的功能。因此,JPEG-2000的硬體架構設計已成為數位相機的關鍵技術。
在這本論文中,我們提出了一個高效能的JPEG-2000 EBCOT方塊編碼器硬體架構。在這個硬體架構之中,我們根據EBCOT演算法的特性,設計了兩種加速方法並使用管線化的技巧。這些加速方式使得方塊編碼器所需的運算週期數可以降低到原本的40%。方塊編碼器可以分為兩個主要部分:context產生器與算術編碼器。在context產生器中,主要的加速想法是將不需要壓縮的點快速的跳過。我們使用以「行」為基礎的運算,並配合兩種加速方式來達成。而在算術編碼器中,則使用了一個四級的管線來降低最長路徑所需的運算時間,並且使用look-ahead的技巧,以達到每一個週期壓縮一組context。
我們完成了一個原型晶片以驗證架構的正確性。此晶片以COMPASS 0.35um標準單元合成,使用台積電0.35um 1P4M製程下線製作,面積是3.67x3.67mm。模擬速度可達50MHz,每秒可處理四百六十萬像素,相當於每秒壓縮一張2400x1800的影像,或是每秒壓縮30張452x340的影片。
As the rapid increase of Internet demanding and the use of digital still camera (DSC), still image is broadly used as a storage and transmission media. JPEG-2000 is a new still image compression standard. It has better compression performance than conventional JPEG standard, and it provides many useful features. The hardware implementation of JPEG-2000, therefore, becomes essential technique of digital still camera.
In this thesis, a high performance hardware architecture design of EBCOT block coder for JPEG-2000 is proposed. Speedup methods and pipelining technique are adopted according to the characteristic of EBCOT block coding algorithm. By using this architecture, process time can be reduced to about 40% of previous work. There are two major parts in this block coder: context formation (CF) and arithmetic encoder (AE). The main idea to improve the process speed of context formation is to skip no-operation samples. We achieve this by column-based coding architecture and two speedup methods. In arithmetic encoder, a four-stage pipeline is used to reduce the clock cycle time. Besides, a look-ahead technique is used in probability table look up to process two identical contexts continuously inputted.
A prototyping chip is implemented to verify the proposed architecture. The technology used is CMOS 0.35um 1P4M technology. The area of this chip is 3.67x3.67 mm2. The clock frequency is 50 MHz. It can encode 4.6 million pixels image within 1 second, corresponding to 2400x1800 image size, or 452x340 video sequence with 30 frames per second. Therefore, this chip is compliant with the upcoming motion JPEG-2000 standard.
CHAPTER 1.INTRODUCTION1
1.1.STILL IMAGE COMPRESSION OVERVIEW1
1.2.TRADITIONAL JPEG SYSTEM3
1.3.JPEG-2000 OVERVIEW5
1.3.1.Discrete Wavelet Transform7
1.3.2.Embedded Block Coding with Optimized Truncation (EBCOT)10
1.4.JPEG-2000 VS. JPEG14
1.5.THESIS ORGANIZATION18
CHAPTER 2.OVERVIEW OF EBCOT BLOCK CODER19
2.1.CONTEXT FORMATION OF BLOCK CODING20
2.1.1.Three coding passes23
2.1.2.Four types of coding operation (primitive)27
2.2.ADAPTIVE CONTEXT-BASED ARITHMETIC ENCODER OF BLOCK CODING31
CHAPTER 3.ANALYSIS AND PROFILING OF JPEG-200036
3.1.JPEG-2000 ANALYSIS AND PROFILING36
3.2.DETAIL ANALYSIS OF EBCOT BLOCK CODER38
3.3.PREVIOUS WORK42
3.3.1.Proposal by David Taubman43
3.3.2.Proposal by Analog Devices Inc.44
3.4.COLUMN-BASED OPERATION AND TWO SPEEDUP METHODS45
3.4.1.Column-based Operation45
3.4.2.Speedup Method 1: Sample Skipping (SS)48
3.4.3.Speedup Method 2: Group-Of-Column Skipping (GOCS)50
CHAPTER 4.ARCHITECTURE DESIGN OF EBCOT BLOCK CODER56
4.1.BLOCK CODING SYSTEM56
4.2.CONTEXT FORMATION57
4.2.1.Column-based Operation and Significant Register PE59
4.2.2.Sample Skipping Speedup Method62
4.2.3.Group-of-Column Skipping63
4.2.4.Memory Arrangements65
4.3.ARITHMETIC ENCODER67
4.3.1.Architecture Comparison70
4.4.PERFORMANCE EVALUATION71
CHAPTER 5.CHIP IMPLEMENTATION76
5.1.DESIGN FLOW76
5.2.TESTING CONSIDERATION78
5.3.CHIP LAYOUT AND SPECIFICATIONS79
CHAPTER 6.CONCLUSION83
BIBLIOGRAPHY85
INDEX88
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