臺灣博碩士論文加值系統

摘要
為了以實地(In-situ)且非破壞方式量測微電子構裝內部所產生的應力分佈與環境溫度及晶片功率的關係，本論文首先以傳統積體電路製程製作P型與N型之壓電阻式應力感測元件，其次藉由量測感測元件在構裝前後的電阻變化及依據壓電阻效應相關理論公式得出測試晶片經構裝後應力分佈與溫度的變化關係。本論文的結果顯示測試晶片在30~130°C溫度範圍內壓電阻應力計之電阻值隨著構裝溫度改變而有明顯的變化。其中N型應力計之構裝應力與溫度變化呈線性關係，但P型應力計因應力係數萃取之偏差頗大，且計算出之應力變化範圍並不合理，所以目前對P型壓電阻應力計的實驗結果只能作為參考。另一方面，本論文也量測到測試晶片之加熱功率與構裝應力間的關係，其應力的變化與應力計距熱源的距離遠近有關，且功率與應力的變化近似線性。從研究的結果顯示，N型摻雜式電阻之壓電阻應力計確實能夠量測
電子構裝之內部應力。

ABSTRACT
The purpose of this article is quantitatively extracting the stress distribution in microelectronics packages through in-situ and non-destructive measurements. To this end, the P-type and N-type piezoresistive stress sensors were first designed and manufactured by conventional IC process. Secondly, the stress sensors were packaged and the resistance variations of the sensors were measured at different temperature so that the relationship between stress distribution and temperature were extracted according to the piezoresistive theorem. The experiment results showed that the resistance of the sensors increased with temperature in the range of 30~130℃. For N-type sensors, linear relationships were derived between stress and temperature. However, since unreasonable results were derived from P-type sensors, further study on P-type sensors will be needed. Experiments on power dissipation from the test chips in package were finally performed, and linear curves were derived between stress and the distance from heater to the sensors. It is concluded that N-type piezoresistive stress sensors are able to extract stress in microelectronics packages with good accuracy.

目錄
1. 緒論…………………………………………………………………1
1.1. 前言…………………………………………………………..1
1.2. 電子構裝的目的與未來趨勢.………………..…………….2
1.3. 電子構裝面臨的問題 .………..………………..…………5
1.4. 論文架構及研究重點..………………………………………6
2. 理論分析……………………………………………………………8
2.1. 簡介…………………………………………………………..8
2.2. 熱阻的定義………………………………………………..…8
2.3. 簡介應力與應變……………………………………………..10
2.3.1. 正向應力與正向應變………………………………….10
2.3.2. 剪應力與剪應變……………………………………….11
2.4. 熱應力產生的因素…………………………………………..12
2.5. 電子構裝結構與易產生應力的位置…….………….………14
2.5.1. QFP構裝結構.………………………………………….14
2.5.2. 電子構裝易產生應力的位置………………………….15
2.6. 熱應力係數的萃取…………………………………………..16
2.6.1. 壓電阻元件設計……………………………………….16
2.6.2. 壓電阻元件理論……………………………………….17
3. 實驗設計與執行….………………………………..…………….20
3.1. 量測簡介…………………………………….……………….20
3.2. 測試晶片的製備…………..…………….…………….21
3.2.1. 設計的理念…………………………………………21
3.2.2. 晶片之製作與晶片構裝……………………………24
3.3. 應力校準………………………………………………….27
3.3.1. 四點彎曲(Four-point bending)校準法…………27
3.3.2. 應力係數之萃取……………………………………29
3.4. 溫度校準…………………………………………..…….30
3.4.1. 溫度校準系統的建立………………………………30
3.4.2. 溫度係數之萃取……………………………………32
3.5. 以測試晶片量測實際的構裝產品 .………….…………33
3.5.1. 實驗實施步驟………………………………………34
3.5.2. 誤差分析……………………………………………38
4. 結果與討論…………………………..……………………………40
4.1. 溫度校準之結果………………………………………….41
4.2. 實際構裝後壓電阻元件的應力效應…………………….47
4.3. 模擬真實晶片工作的應力效應………………………….55
5. 結論 ………………..…………………………………………….63
參考文獻……………………………………………………………….65
自傳…………………………………………………………………….67

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