臺灣博碩士論文加值系統

本篇論文設計了可以計算128/256/512/1024/2048的可變長度快速傅立葉轉換處理器晶片，這顆晶片採用單一路徑延遲迴授(single-path delay feedback)的管線(pipeline)架構配合Radix-2^3演算法來做設計，並且透過系統模擬來決定表示資料所需的位元數，以達到正交分頻多工傳輸系統的需求。除此之外，我們提出了一個迴授旋轉因子產生器用來替代存放旋轉因子儲值表(lookup table)，以節省所需的記憶體空間。
在使用CMOS 0.35μm 2P4M製程的情況下，我們的快速傅立葉轉換處理器其核心面積只有3.381 x 3.3625 mm^2，而且經過後佈局模擬(post-layout simulation)，證明輸出的資料速率至少可達到22.72 MHz以上，可符合IEEE 802.16e標準的需求。

　　A single chip of variable length FFT processor is presented in this thesis. This processor can be applied for the applications with 128/256/512/1024/2048-point FFT. This processor is based on SDF (single path delay feedback) pipeline architecture with radix-2^3 computation element. The number of bits for input data and twiddle factors is carefully selected by system simulation to meet the requirements of OFDM system. In addition, we propose a feedback twiddle factor generator to instead the lookup table for twiddle factors to reduce the storage size of memory.
The FFT processor is carried out by CMOS 0.35μm 2P4M process with core area 3.381x3.3625 mm^2. In the gate level simulation, the output data rate of this FFT processor is above 22.72MHz, so the processor can meet the requirement of IEEE 802.16e standard.

誌謝 i
摘要 ii
Abstract iii
圖索引 vi
表索引 viii
第一章　簡介 1
第二章　快速傅立葉轉換演算法及硬體架構 4
2.1　分時、分頻快速傅立葉轉換 4
2.1.1 分時快速傅立葉轉換 4
2.1.2分頻快速傅立葉轉換 7
2.2　Radix-2/4/8 分時快速傅立葉轉換 10
2.3　Radix-23 分時快速傅立葉轉換 15
2.4 Radix-24 分時快速傅立葉轉換 18
2.5 快速傅立葉轉換演算法選擇說明 21
2.5.1 各種FFT演算法所需要的複數乘法器 21
2.6 記憶體式（Memory-based）快速傅立葉轉換架構 26
2.7 管線（Pipeline）快速傅立葉轉換架構 27
2.7.1 Radix-2多路徑換向 27
2.7.2 Radix-2單一路徑延遲迴授 30
2.7.3 硬體架構選擇說明 34
第三章　可變長度快速傅立葉轉換電路設計 35
3.1 基本元件設計 35
3.1.1　Radix-2 單一路徑延遲迴授架構和運算元件 35
3.1.2　乘法器等效元件 36
3.2　128/256/512/1024/2048點可變長度FFT架構 38
3.3　迴授旋轉因子產生器 40
第四章　系統模擬和晶片設計流程 46
4.1 硬體需求 46
4.2　晶片設計流程 50
4.2.1　加入可測試性設計 55
4.2.2　佈局和繞線 57
4.2.3　DRC和LVS驗證 57
4.2.4　Nanosim模擬結果 59
第五章　結論 61
參考文獻 63

[1] A. V. Oppenheim R.W. Schafer, "Discrete-Time Signal Processing," Prentice- Hall, Second Edition 1999.
[2] B. R. Salzberg, "Performance of an efficient parallel data transmission system," IEEE Trans. Commun., vol. 15, pp. 805-811, Dec. 1967.
[3] S. B. Weinstein and P. M. Ebert, "Data transmission by frequency division multiplexing using the discrete Fourier transform," IEEE Trans. Commun., vol. 19, pp. 628-634, Oct. 1971.
[4] J. W. Cooley and J. W. Turkey, "An algorithm for the machine calculation of complex Fourier series," Math. Comp., pp. 297-301, 1965.
[5] G. D. Bergland, "A fast Fourier transform algorithm using base 8 iterations," Math. Comp., pp. 275-279, 1968.
[6] Y.-T. Lin, P.-Y. Tsai and T.-D. Chiueh, "Low-power variable-length fast Fourier transform processor," IEE Proc.-Comput. Digit. Tech., vol. 152, no.4, July 2005
[7] Y. Ma., "An effective memory addressing scheme for FFT processors," IEEE Trans. Signal Processing, vol. 47 issue:3, pp. 907-911, March 1999.
[8] S. He and M. Torkelson, "A new approach to pipeline FFT processor," IEEE Int. Symp. Circuits and Systems, pp. 766-776, 1996.
[9] Y.-W. Lin, H.-Y. Liu, and C.-Y. Lee, "A dynamic scaling FFT processor for DVB-T applications," IEEE J. Solid-State Circuit, vol. 39, pp. 2005-2013, Nov. 2005.
[10] K. Maharatna, E. Grass, and U. Jagdhold, "A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM," IEEE J. Solid-State Circuits, vol. 39, no. 3, March 2004.
[11] E. Chu and A. George, "Inside the FFT block box," CRC Press LLC, ch.11, 2000.
[12] A. Wenzler and E. Luder, "New structures for complex multipliers and their noise analysis," IEEE Int. Symp. Circuits and Systems, vol.2, pp.1432-1435, May 1995.
[13] C.-S. Wu, A.-Y. Wu, and C.-H. Lin, "A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes," IEEE Trans. Circuits and Systems, vol. 50, pp. 589-601, Spet. 2003.
[14] B.M. Bass, "A low-power, high-performance, 1024-point FFT processor," IEEE J. Solid-State Circuits, vol. 34, pp.380-387, Mar. 1999.
[15] S. He and M. Torkelson, "Design and implementation of a 1024-point pipeline FFT processor," IEEE Custom Int. Circuits Conf., pp.7.5.1-7.5.4,1998.
[16] W.-C Yeh and C.-W. Jen, "High-speed and low-power split-radix FFT," IEEE Trans. Signal Processing, vol. 51, pp.864-874, Mar. 2003.
[17] C.-K Chang, C.-P. Hung, and S.-G. Chen, "An efficient memory-based FFT architecture," IEEE Int. Symp. Circuit and System, vol. 2, May 2003.
[18] S. Lee, H. Kim, and S.-C. Park, "Design of power-efficient memory-based FFT processor with new memory addressing scheme," IEEE Conf. Commun., pp.1-5, Aug. 2006.
[19] J.-Y. Oh and M.-S. Lim, "Area and power efficient pipeline FFT algorithm," IEEE Workshop on Signal Processing Systems Design and Implementation, pp.520-525, Nov. 2005.
[20] J. Lee, H. Lee, S.-I. Cho, and S.-S Choi, "A high-speed, low complexity radix-24 FFT processor for MB-OFDM UWB system," IEEE Int. Symp. Circuits and Systems, pp.4719-4722, May 2006.
[21] E. Horowitz and A. Zorat, "Divide-and-conquer for parallel processing," IEEE Trans. Computers, vol. c-32, pp.582-585, Jun. 1983.
[22] N.-H. Chang, "Cell-based IC physical design and verification with SOC Encounter," National Chip Implementation Center, R.O.C., July 2005.
[23] L. Jia, Y. Gao, J. Isoaho, and H. Tenhunen, "A new VLSI-oriented FFT algorithm and implementation," IEEE ASIC. Conf., pp.337-341, 13-16 Sept. 1998.
[24] R. Olexa, "Implementing 802.11, 802.16, and 802.20 wireless networks," Elsevier,2005.
[25] D. Sweeney, "WiMax operator’s manual," Appress, Second Edition 2006.
[26] http://www2.cic.org.tw/~shuttle/drc/t35ms/index.html
[27]　L.R. Rabiner and B. Gold., "Theory and Application of Digital Signal Processing," Prentice- Hall, 1975.
[28] European Telecommunication Standard Institute, "Digital Video Broadcasting (DVB); Framing structure channel coding and modulation for digital terrestrial television (DVB-T)," ETSI document, EN 300 744 v1.5.1, November 2004.