臺灣博碩士論文加值系統

中文摘要
電子構裝體在嚴苛規格的挑戰下，新一代覆晶構裝方法為提高可靠度，必須致力於避免因缺陷所衍生的破裂失效。界面間出現的脫層現象，係由於界面間應力集中甚至應力奇異性的結果；在凸塊、填料乃至晶片都可能因界面脫層現象而導致裂縫的產生，以至構裝體的最後失效。
本文在以有限元素模式模擬覆晶構裝體的方法下，研究在循環溫度負載情況時，以參數分析架構探討影響脫層失效的關鍵因素。吾人利用此發展完成的模式，在應力集中情況以及熱膨脹係數之參數變化分析獲得證實的情況下，相較於調整填料熱膨脹係數以及改變填角幾何形狀這兩種參數分析，本研究獲致以晶片圓弧轉角是降低界面脫層應力、和緩應力集中程度、分散應力集中點的有效措施之一的結論。在此改善應力集中的措施下，定可降低脫層失效機率以提昇覆晶構裝體之可靠度。

Abstract
Under the stringent specification for the microeletronic packages, higher product’s reliability was quested by the prevention from fatigue/fracture failure of the new generation of Flip-Chip assembly due to the existence of defects. The delamination on the assembly’s interfaces is owing to the effects of stress concentration and/or stress singularity; and solder bumps, underfill, chip may therefore induce cracks as the precursor of a final stage failure.
Flip-Chip Packages under thermal cyclic loading had been simulated by the finite element method in this research. The key factors to contribute the delamination on the package’s interfaces had been studied through the process of parametric analysis. A finite element model was developed under this methodology, and the applications of this model confirmed that the locations of stress concentration were indeed at the corner or the edge of chip and the interfacial stresses were proved correctly as proportional with coefficient of thermal expansion of underfill material. Based on the comparison among the variation of three different parameters: (1) coefficient of thermal expansion of underfill, (2) geometric size of underfill’s fillet, (3) rounded corner of chip, it was concluded that a rounded corner of chip was an effective measure to lower the critical stresses of delamination on interfaces, as well as to ease the magnitude and sensitive location of stress concentration. With this measure in effect, the reliability of Flip-Chip packages can be improved by eliminating the possibility of interfacial delamination.

目錄
摘要 頁次
第一章 緒論 1
1-1 文獻回顧 2
1-2 研究目的與方法 8
第二章 模擬建構與分析策略 22
2-1 基本假設 22
2-2 參數設定與分析策略 23
2-3 分析步驟 23
第三章 結果與討論 38
3-1 填料熱膨脹係數對界面應力狀態之敏感度分析 38
3-2 填角型態對界面應力狀態之敏感度分析 39
3-3 圓弧轉角晶片對界面應力之敏感度分析 40
3-3 三種變化參數對界面應力敏感度之比較分析 40
第四章 結論 48
參考文獻 50
表目錄
表2.1 材料之結構性質及熱傳性質 15
表2.2 63%Sn/37%Pb凸塊材料之應力應變關係 16
表3.1 三種參數變化在各界面最大應力之影響排序 32
圖目錄
圖1.1 覆晶構裝示意圖 6
圖1.2 凸塊承受的應力、變形與可能破裂處之示意圖 6
圖2.1 晶片之幾何型態參數 17
圖2.2 SOLID70三維熱傳分析元素 17
圖2.3 覆晶構裝模型 18
圖2.4 凸塊模型 18
圖2.5 ANSYS網格分割圖 19
圖2.6 熱傳分析邊界條件 19
圖2.7 循環溫度時程圖 20
圖2.8 二次循環之最大剝離正向應力時程圖 20
圖2.9 SOLID45三維結構分析元素 21
圖2.10等向性硬化設定 21
圖2.11複線性等向硬化表示圖 22
圖2.12複線性等向硬化之應力應變關係圖 22
圖2.13結構分析邊界條件 23
圖2.14各界面間位置與長度分佈圖 23
圖2.15晶片/填料界面間之XY方向最大剪應力對位置分佈曲線 24
圖2.16晶片/填料界面最大剪應力對溫度之分佈圖 24
圖3.1 晶片/填料界面最大剝離正向應力對溫度之分佈圖 33
圖3.2 晶片/填料界面最大剝離正向應力作用位置對溫度之分佈圖 33
圖3.3 晶片/填料界面最大剪應力對溫度之分佈圖 34
圖3.4 晶片/填料界面最大剪應力作用位置對溫度之分佈圖 34
圖3.5 晶片/填角界面最大剝離正向應力對溫度之分佈圖 35
圖3.6 晶片/填角界面最大剝離正向應力作用位置對溫度之分佈圖 35
圖3.7 晶片/填角界面最大剪應力對溫度之分佈圖 36
圖3.8 晶片/填角界面最大剪應力作用位置對溫度之分佈圖 36
圖3.9 填角/基板界面大剝離正向應力對溫度之分佈圖 37
圖3.10填角/基板界面最大剝離正向應力作用位置對溫度之分佈圖 37
圖3.11填角/基板界面最大剪應力對溫度之分佈圖 38
圖3.12填角/基板界面最大剪應力作用位置對溫度之分佈圖 38
圖3.13晶片/填料界面最大剝離正向應力敏感度趨勢圖 39
圖3.14晶片/填料界面最大剪應力敏感度趨勢圖 39
圖3.15晶片/填角界面最大剝離正向應力敏感度趨勢圖 40
圖3.16晶片/填角界面最大剪應力敏感度趨勢圖 40
圖3.17填角/基板界面最大剝離正向應力敏感度趨勢圖 41
圖3.18填角/基板界面最大剪應力敏感度趨勢圖 41
圖3.19晶片/填料界面最大剝離正向應力對溫度之分佈圖 42
圖3.20晶片/填料界面最大剝離正向應力作用位置對溫度之分佈圖 42
圖3.21晶片/填料界面最大剪應力對溫度之分佈圖 43
圖3.22晶片/填料界面最大剪應力作用位置對溫度之分佈圖 43
圖3.23晶片/填角界面最大剝離正向應力對溫度之分佈圖 44
圖3.24晶片/填角界面最大剝離正向應力作用位置對溫度之分佈圖 44
圖3.25晶片/填角界面最大剪應力對溫度之分佈圖 45
圖3.26晶片/填角界面最大剪應力作用位置對溫度之分佈圖 45
圖3.27填角/基板界面大剝離正向應力對溫度之分佈圖 46
圖3.28填角/基板界面最大剝離正向應力作用位置對溫度之分佈圖 46
圖3.29填角/基板界面最大剪應力對溫度之分佈圖 47
圖3.30填角/基板界面最大剪應力作用位置對溫度之分佈圖 47
圖3.31晶片/填料界面最大剝離正向應力敏感度趨勢圖 48
圖3.32晶片/填料界面最大剪應力敏感度趨勢圖 48
圖3.33晶片/填角界面最大剝離正向應力敏感度趨勢圖 49
圖3.34晶片/填角界面最大剪應力敏感度趨勢圖 49
圖3.35填角/基板界面最大剝離正向應力敏感度趨勢圖 50
圖3.36填角/基板界面最大剪應力敏感度趨勢圖 50
圖3.37晶片/填料界面最大剝離正向應力對溫度之分佈圖 51
圖3.38晶片/填料界面最大剝離正向應力作用位置對溫度之分佈圖 51
圖3.39晶片/填料界面最大剪應力對溫度之分佈圖 52
圖3.40晶片/填料界面最大剪應力作用位置對溫度之分佈圖 52
圖3.41晶片/填角界面最大剝離正向應力對溫度之分佈圖 53
圖3.42晶片/填角界面最大剝離正向應力作用位置對溫度之分佈圖 53
圖3.43晶片/填角界面最大剪應力對溫度之分佈圖 54
圖3.44晶片/填角界面最大剪應力作用位置對溫度之分佈圖 54
圖3.45填角/基板界面大剝離正向應力對溫度之分佈圖 55
圖3.46填角/基板界面最大剝離正向應力作用位置對溫度之分佈圖 55
圖3.47填角/基板界面最大剪應力對溫度之分佈圖 56
圖3.48填角/基板界面最大剪應力作用位置對溫度之分佈圖 56
圖3.49晶片/填料界面最大剝離正向應力敏感度趨勢圖 57
圖3.50晶片/填料界面最大剪應力敏感度趨勢圖 57
圖3.51晶片/填角界面最大剝離正向應力敏感度趨勢圖 58
圖3.52晶片/填角界面最大剪應力敏感度趨勢圖 58
圖3.53填角/基板界面最大剝離正向應力敏感度趨勢圖 59
圖3.54填角/基板界面最大剪應力敏感度趨勢圖 59
圖3.55晶片/填料界面最大剝離正向應力敏感度趨勢圖 60
圖3.56晶片/填料界面最大剪應力敏感度趨勢圖 60
圖3.57晶片/填角界面最大剝離正向應力敏感度趨勢圖 61
圖3.58晶片/填角界面最大剪應力敏感度趨勢圖 61
圖3.58填角/基板界面最大剝離正向應力敏感度趨勢圖 62
圖3.60填角/基板界面最大剪應力敏感度趨勢圖 62

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