臺灣博碩士論文加值系統

為了延伸莫爾定律，三維堆疊的積體電路（3D-IC）已被視為未來發展的明日之星。然而，基於矽穿孔(Through Silicon Via, TSVs)作為內連線的3D-IC良率仍然不高，因此TSVs的測試和修復方法成為重要的課題。雖然許多的TSVs修復方式已經被提出來，但是很少提到關於TSVs軟性錯誤修復方式，而TSVs的軟性錯誤經常以叢聚型的情況發生。因此本論文利用ECC搭配所提出的演算法來處理TSVs通道所發生的叢聚型錯誤，而ECC的錯誤旗標可以用來監控並替換老化的TSVs。
　　實驗的結果表明，提出的方法可以有效地將TSVs的MTBR提高達〖10〗^3倍，搭配的2DPC解碼器可以將錯誤在1.72奈秒更正。與先前的文獻做比較在相同大小的TSVs陣列中可以更正四倍大的叢聚型錯誤。

關鍵字 — 矽穿孔、叢聚型錯誤、錯誤更正碼、監控

In order to extend Moore's Law, three-dimensional stacked integrated circuits (3D-IC) has been seen as a new solution. However, the yield of 3D-IC base on through silicon via(TSV) is still now high. Therefore, TSVs testing and repair methods has become an important issue. Although many of TSVs repair methods have been proposed, but little mention of the symptoms of aging on TSVs soft error monitoring and repair methods.
In this paper, we propose an ECC algorithms to deal with the cluster error occurred in TSVs channel. Experiments show that the proposed method can effectively improve about 103 times of MTBR, and 2DPC decoder can correct errors in the 1.72 ns. Comparing with the previous work the proposed method can correct four times of cluster errors in the same size of TSVs array.

Keywords : TSVs、Cluster-error、ECC、Aging monitor.

中文摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章、 緒論 1
1-1 研究背景 1
1-2 研究動機與目的 1
1-3 本論文所使用架構 3
第二章、 適用於矽穿孔陣列之叢聚型錯誤模型 4
2-1 矽穿孔硬體故障 4
2-2 叢聚型錯誤 8
2-3 叢聚型錯誤模型 9
2-3-1 「先事件定位(Pre-Event Locating)」條件機率式叢聚型錯誤事件模型 11
2-3-2 「後事件定位(Post-Event Locating)」條件機率式叢聚型錯誤事件模型 12
第三章、 文獻中針對軟性錯誤的解決方法 14
3-1 單一錯誤更正碼 14
3-2 漢明碼(Hamming code) 15
3-3 二維同位元檢測碼2DPC(Two Dimension Parity Check Code) 21
3-4 適用於多位元錯誤更正的演算法及線上即時監控架構 24
3-4-1 用於解決叢聚型錯誤之矩陣碼 24
3-4-2 雙餘數編碼(bi-residue) 26
第四章、 線上即時更正叢聚型錯誤的演算法 28
4-1 基於SEC所提出的演算法 28
4-1-1 1D SEC搭配滑動演算法 29
4-1-2 1D SEC+1D SED座標變換演算法 30
4-2 各種演算法之比較 34
第五章、 實驗結果 36
5-1 所使用的SEC編解碼時間 36
5-1-1 編解碼時間比較 36
5-1-2 面積開銷比較 38
5-2 區塊錯誤率分析 40
5-2-1 區塊錯誤率實驗結果 40
第六章、 結論 42
參考文獻 43
作者簡歷 44

[1] U. Kang, H. J. Chung, S. Heo, D. H. Park, H. Lee, J. H. Kim, S. H. Ahn, S. H. Cha, J. Ahn, D. Kwon, J. W. Lee, H. S. Joo, W. S. Kim, D. H. Jang, N. S. Kim, J. H. Choi, T. G. Chung, J. H. Yoo, J. S. Choi, C. Kim, and Y. H. Jun, “8 Gb 3-D DDR3 DRAM using through-silicon-via technology,” Ieee Journal of Solid-State Circuits, vol. 45, pp. 111-119, Jan 2010.
[2] H. H. S. Lee and K. Chakrabarty, “Test challenges for 3D integrated circuits, ” Ieee Design & Test of Computers, vol. 26, pp. 26-35, Sep-Oct 2009.
[3] C. Chun-Chuan, W. Cheng-Wen, W. Min-Jer, and L. Hung-Chih, “3D-IC interconnect test, diagnosis, and repair, ” in VLSI Test Symposium (VTS), 2013 Ieee 31st, pp. 1-6.
[4] H. Ang-Chih, H. TingTing, C. Ming-Tung, T. Min-Hsiu, T. Chih-Mou, and L. Hung-Chun, “TSV redundancy: Architecture and design issues in 3D IC, ” in Design, Automation & Test in Europe Conference & Exhibition 2010, pp. 166-171.
[5] H. Yu-Jen and L. Jin-Fu, “Built-in self-repair scheme for the TSVs in 3-D ICs, ” Computer-Aided Design of Integrated Circuits and Systems, Ieee Transactions on, vol. 31, pp. 1600-1613, 2012.
[6] H. Tsung-Chu, “High-performance built-in self-routing for through-silicon vias, ” Electronics Letters, vol. 48, pp. 480-482, 2012.
[7] M. Pflanz, K. Walther, C. Galke, and H. T. Vierhaus, “On-line error detection and correction in storage elements with cross-parity check, ” in On-Line Testing Workshop, Proceedings of the Eighth Ieee International, 2002, pp. 69-73.
[8] C. Chang-Hsin, L. Chung-Kai, L. Hsing-Chuang, and J. Kung-Ming, “On-line error detection and correction techniques for TSV in three-dimensional integrated circuit, ” in Intelligent Signal Processing and Communications Systems (ISPACS), International Symposium on, 2011, pp. 1-5.
[9] J. Li, X. Qiang, and B. Eklow, “On effective through-silicon via repair for 3-D-stacked ICs, ” Computer-Aided Design of Integrated Circuits and Systems, Ieee Transactions on, vol. 32, pp. 559-571, 2013.
[10] M. Blaum and P. G. Farrell, “Array codes for cluster-error correction, ” Electronics Letters, vol. 30, pp. 1752-1753, 1994.
[11] P. Calingaert, “Two-dimensional parity checking, ” J. ACM, vol. 8, pp. 186-200, 1961.
[12] M. Blaum and R. M. Roth, “New array codes for multiple phased burst correction, ” Information Theory, Ieee Transactions on, vol. 39, pp. 66-77, 1993.
[13] R. Naseer and J. Draper, “Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs, ” in Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European, 2008, pp. 222-225.