|
[1]S. Nastic, et al., “Provisioning Software-Defined IoT Cloud Systems,” Future Internet of Things and Cloud (FiCloud), pp.288-295, Aug. 2014. [2]W.C. Lee, et al., “Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling,” IEEE Transactions on Electron Devices, vol.60, no. 6, pp.1814-1819, June 2013. [3]C.Y. Lu, et al., “Reverse short-channel effects on threshold voltage in submicrometer salicide devices,” IEEE Electron Device Letters, vol.10, no.10, pp.446-448, Aug.2002. [4]M. Suetake, et et al., “Precise physical modeling of the reverse-short-channel effect for circuit simulation,”IEEE Simulation of Semiconductor Processes and Devices, pp.207-210, Sep.1999. [5]S. Chaudhuri, et al., “ FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage,” IEEE 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, pp.476-482, Jan.2014. [6]F. He, et al., “FinFET: From compact modeling to circuit performance,” IEEE Electron Devices and Solid-State Circuits (EDSSC), pp.1-6, Dec.2010. [7]J. D. Meindl, et al., “Beyond Moore's Law: the interconnect era,” IEEE Computing in Science & Engineering, vol. 5, no. 1, pp. 20-24, Jan.2003. [8]劉傳璽、陳進來,“半導體元件物理與製程”,五南出版社,2011年。 [9]T. Meyer, et al., “A Theory of Packet Flows Based on Law-of-Mass-Action Scheduling,” IEEE Reliable Distributed Systems (SRDS), pp. 341-351, Oct. 2012 [10]A. R. Brown, et al., “Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability: A 3-D simulation study,” IEEE 2016 European Solid-State Device Research Conference, pp.451-454, Spet. 2006. [11]M. Fukuma, et al., “Cross-section space charge measurement system,” IEEE Solid Dielectrics, 2004. ICSD, vol. 1, pp.182-185, July. 2004. [12]K. Uchida, et al., “Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETs,” IEEE International Electron Devices Meeting (IEDM), pp. 229-232, Dec. 2004. [13]T. Rudenko, et al., “Carrier Mobility in Undoped Triple-Gate FinFET Structures and Limitations of Its Description in Terms of Top and Sidewall Channel Mobilities,” IEEE Transactions on Electron Devices, vol. 55, no. 12, pp. 3532-3541, Dec. 2008. [14]J. Sudhakar, et al., “Exhaustive analysis & behavior of nanometer MOSFET for threshold voltage variations,” IEEE International Signal Processing, Communication and Networking (ICSCN), pp. 1-6, Mar. 2015. [15]S. Zafar, et al., “Threshold voltage instabilities in high-κ gate dielectric stacks,” IEEE Transactions on Device and Materials Reliability, vol. 5, no. 1, pp. 45-64, Mar. 2005. [16]T. Numata, et al., “Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs,” IEEE Transactions on Electron Devices, vol. 51, no. 12, pp. 2161-2167, Dec. 2004. [17]E. P. Vandamme, et al., “Modeling the subthreshold swing in MOSFET's,” IEEE Electron Device Letters, vol. 18, no. 8, pp. 369-371, Aug. 1997. [18]S. Maeda, et al., “Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET's,” IEEE Transactions on Electron Devices, vol. 46, no. 1, pp. 151-158, Jan. 1999. [19]Y. C. Tseng, et al., “AC floating body effects and the resultant analog circuit issues in submicron floating body and body-grounded SOI MOSFET's,” IEEE Transactions on Electron Devices, vol. 46, no. 8, pp. 1685-1692, Aug. 1999. [20] V. N. Obreja, et al., “Leakage current voltage dependence and performance of power semiconductor devices in the breakdown (avalanche) region,” IEEE Power Electronics Specialists Conference, pp. 1777-1782 , June. 2008. [21]A. Aditya, et al., “Threshold voltage roll-off for triple gate FinFET analysis based on several semiconductors used as substrate,” IEEE High Performance Computing and Applications (ICHPCA), pp. 1-6, Dec. 2014. [22]N. Damrongplasit, et al., “Threshold Voltage and DIBL Variability Modeling Based on Forward and Reverse Measurements for SRAM and Analog MOSFETs,” IEEE Transactions on Electron Devices, vol. 62, no. 4, pp. 1119-1126, Apr. 2015. [23]M. F. Al-Mistarihi, et al., “Drain induced barrier lowering (DIBL) accurate model for nanoscale Si-MOSFET transistor,” IEEE International Conference on Microelectronics (ICM), pp. 1-4, Dec. 2013. [24]F. Capasso, et al., “Interdigitated pn junction device with novel capacitance/voltage characteristic, ultralow capacitance and low punch-through voltage,” Institution of Engineering and Technology (IET), vol. 18, no. 18, pp. 760-761, Sept. 2007. [25]http://www.mem.com.tw/article_content.asp?sn=1402260021 [26]http://www.mem.com.tw/article_content.asp?sn=1309060004 [27]鄭晃忠、劉傳璽,“新世代積體電路製程技術”,交通大學出版社,2013年。 [28]施敏、李明逵,“半導體元件物理與製程技術”,交通大學出版社,2013年。 [29]http://www.eetimes.com/document.asp?doc_id=1280773 [30]S. Flachowsky, et al., “Understanding Strain-Induced Drive-Current Enhancement in Strained-Silicon n-MOSFET and p-MOSFET,” IEEE Transactions on Electron Devices, vol. 57, no. 6, pp.1343-1354, June. 2010. [31]Q. H. Han, et al., “Challenges and solutions to FinFET gate etch process,” IEEE Semiconductor Technology International Conference (CSTIC), pp.1-3. Mar. 2015. [32]S. Pae, et al., “Multi-layer SOI island technology by selective epitaxial growth for single-gate and double-gate MOSFETs,” IEEE SOI Conference, pp. 108-109, Oct. 1999. [33]G. A. Brown, et al., “Integrity of gate oxides formed on SIMOX wafers,” IEEE SOI Conference, pp. 73-74, Oct. 1994. [34]A. Valletta, et al., “Analysis of Kink Effect and Short Channel Effects in Fully Self-Aligned Gate Overlapped Lightly Doped Drain Polysilicon TFTs,” IEEE Journal of Display Technology, vol. 9, no.9, Sept. 2013 [35]W. S. Liao, et al., “Investigation of Reliability Characteristics in NMOS and PMOS FinFETs,” IEEE Electron Device Letters, vol. 29, no. 7, July. 2008. [36]W. S. Liao, et al., “A novel high aspect ratio FinFET with cobalt fully silicided gate structure,” IEEE VLSI-TSA International Symposium on VLSI Technology, pp.114-115, Apr. 2005. [37]M.C. Wang, et al., “Nano-scale Si-capping thicknesses impacting junction performance on <110> silicon substrate,” IEEE Nanoelectronics Conference (INEC), pp. 1-2, June. 2011.
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