臺灣博碩士論文加值系統

影像編碼系統的設計與製作是本論文的研究主題。我們以三個主要的影像編碼標準─JPEG，JPEG 2000，與MPEG-4 VTC─為研究實例，針對影像壓縮演算法的特性，分別提出特製化的硬體架構設計，以提升執行效率。我們提出了全管線式JPEG編碼器與解碼器的架構，每個週期可以處理一個取樣資料，也就是在50 MHz的工作頻率之下，可以處理五千萬個資料點，這樣的高效能架構，滿足數百萬畫素等級數位相片的快速編解碼規格。此外，整體架構的特色在於完整性，可以不需額外處理器的協助，獨立完成JPEG編碼與解碼。其中，我們針對泛用解碼器提出了支援使用者自訂的霍夫曼表的解碼功能，以應付不同來源的JPEG檔案的解壓縮。針對新一代的影像壓縮標準JPEG 2000，我們深入分析其中最為複雜的EBCOT演算法，提出方塊編碼與解碼的加速引擎，提升位元層級 (bit-level) 運算的效能。此外，進一步提出EBCOT Tier-2的硬體架構，並且藉由EBCOT Tier-2的資訊迴授，可以隨著壓縮倍率的提昇，大幅減少EBCOT的運算量。另一個與JPEG 2000演算法類似的MPEG-4視覺材質編碼 (Visual Texture Coding) 技術，同樣採用離散小波轉換與算數編碼技術，我們針對其中的零樹 (zero-tree) 編碼架構作最佳化設計，特製化位址產生器及控制，以達成流暢的資料流與大量的資料存取。這些高效能的特製化硬體架構設計，對於後PC時代電子產品的高速影像處理功能需求，提供了最具競爭力的方案。

In this dissertation, the hardware architecture design and implementation of image coding systems
are presented. The research focuses on three image coding standards: JPEG, JPEG2000, and MPEG-4
Visual Texture Coding (VTC).
JPEG is a well-known and matured standard. It has been widely used for natural image compression,
especially very popular for digital still camera applications. In the first part of this
dissertation, we proposed fully pipelined JPEG encoder and decoder for high speed image
processing requirements in post-PC electronic appliances. The processing power is 50 million
samples per second at 50 MHz working frequency. The proposed architectures can handle
million-pixel digital images'''''''' encoding and decoding in very high speed. Other feature is that
both the encoder and decoder are stand-alone and full-function solutions. They can encode or
decode the JPEG compliant file without any aids from extra processor.
JPEG2000 is the latest image coding standard. It is defined to be a more powerful standard after
JPEG. JPEG2000 provids better compression performance, especially at low bitrates. It also
provides various features, such as quality and resolution progressive, region of interest coding,
lossy and lossless coding in an unified framework, etc. The performance of JPEG2000 comes at the
cost of higher computational complexity. In the second part of the dissertation, we discuss the
challenges and issues of the design of a JPEG2000 coding system. Cycle efficient block encoding
and decoding engines, and computation reduction techniques by Tier-2 feedback are proposed for
the most critical module, Embedded Block Coding with Optimized Truncation (EBCOT). With the
proposed parallel checking and skipping-based coding schemes, the scanning cycles can be reduced
to 40% of the direct bit-by-bit implementation. As for the Tier-2 feedback control in lossy
coding mode, the execution cycles and therefore power consumption can be lowered to 50% in the
case of about 10 times compression.
MPEG-4 Visual Texture Coding (VTC) tool is another compression algorithm that also adopts the
wavelet-based algorithm. In VTC, Zero-tree coding algorithm is adopted to generate the context
symbols for arithmetic coder. In the third part, the design of the zero-tree coding algorithm is
discussed. Tree-depth scan with multiple quantization mode are realized. Dedicated data access
scheme are designed for smooth coding flow.
In each chapter, detailed analysis of the algorithms are provided first. Then, efficient hardware
architectures are proposed exploiting special algorithm characteristics. The proposed dedicated
architectures can greatly improve the processing performance compared with a general
processor-based solution. For non-PC consumer applications, these architectures are more
competitive solutions for cost-efficient and high performance requirements.

摘 要
第一章 簡 介
第二章 全管線式JPEG編碼器與解碼器系統架構設計
第三章 JPEG 2000演算法分析暨硬體加速與運算減量架構設計
第四章 MPEG-4視覺材質編碼之零樹編碼架構設計
第五章 結 論

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