臺灣博碩士論文加值系統

本篇論文主要描述一個低功率、12位元、操作頻率在50MHz而工作電壓在3.3V的管流式類比數位轉換器之設計，並提出一個內建類比式自我校正電路架構以達到影像處理所需較低的微分、積分非線性特性。有別於一般的數位自我校正系統，本架構不需要龐大且複雜的數位電路，取而代之的是自我校正電容陣列與訊號線性區保護架構。本轉換器採用標準0.35um 2P4M CMOS製程，總功率消耗為148mW，佈局面積約為2.3mm×2.2mm，完整的測試報告將由日後提出。

This thesis describes a design of a low-power, 12-bit, 50Msample/s, and 3.3-V supply pipeline analog-to-digital converter (ADC). In order to achieve the requirements of digital imaging, where differential nonlinearity (DNL) and integral nonlinearity (INL) are both important, we propose a built-in analog self-calibrated circuit of the ADC in this thesis. Compared with the ADC with the typical digital error correction architecture, our circuit does not need a large and complex digital circuit, but they are replaced by the self-calibration capacitor array and linear-range protection architecture. The entire circuit will be fabricated in a 0.35-um 2P4M CMOS process, the estimated chip area is 2.3×2.2mm2, and the power dissipation is 148mW. Final test results will be reported later.

CONTENTS
Page
ABSTRACT (in Chinese) …………………………………………………I
ABSTRACT (in English) …………………………………………………II
ACKNOWLEDGEMENT ………………………………………………III
CONTENTS ………………………………………………………………IV
LIST OF FIGURES ……………………………………………………VII
LIST OF TABLES ……………………………………………………XI


CHAPTER 1 INTRODUCTION ………………………………………1
1.1 Motivation ………………………………………………………1
1.2 Organization ………………………………………………………2

CHAPTER 2 A/D CONVERTER ARCHITECTURES ………………3
2.1 Introduction ………………………………………………………3
2.2 Flash A/D Converter ……………………………………………4
2.3 Delta-Sigma A/D Converter ……………………………………4

CHAPTER 3 THE BUILDING BLOCKS OF A TYPICAL
1.5-BIT/STAGE PIPELINE
A/D CONVERTER ………………………………………7
3.1 Introduction ………………………………………………………7
3.2 Sample & Hold Circuit …………………………………………7
3.3 Sub ADC and Sub DAC …………………………………………9
3.4 Timing Control of Switches ……………………………………10
3.5 Digital Circuit …………………………………………………13

CHAPTER 4 THE DESIGN OF A BUILT-IN ANALOG
SELF-CALIBRATED PIPELINE A/D
CONVERTER …………………………………………15
4.1 Introduction ……………………………………………………15
4.2 The Advantage of Analog Self-Calibrated Pipeline ADC ………15
4.3 Timing Distribution ……………………………………………16
4.4 Nonlinearity Analysis …………………………………………17
4.5 Building Blocks of the Analog Self-Calibrated Pipeline
ADC ……………………………………………………………19
4.6 Design Specification ……………………………………………20
4.6.1 Choice of Capacitors’ Size ………………………………21
4.6.2 Speed Requirement of the Opamp in First Stage ………23
4.6.3 Power Consumption Estimation …………………………24
4.7 1-Bit Multiply-by-two Stage Design ……………………………25
4.7.1 Opamp Design ……………………………………………25
4.7.2 Transient Analysis and SC-CMFB Circuit Design ………27
4.7.3 Dynamic Comparator Design ……………………………31
4.7.4 Double-Side Bootstrapped Switch Design ……………31
4.7.5 1-bit Stage Simulation Result ……………………………33
4.8 Unity-Gain Stage Design ………………………………………38
4.8.1 Unity-Gain Stage Architecture …………………………38
4.8.2 DNL Analysis of Unit Gain Stage ………………………40
4.8.3 Unity-Gain Stage Configuration and Simulation
Result ……………………………………………………41
4.9 2-Bit Flash ADC Design ………………………………………44
4.10 Full ADC Simulation without Gain Error
Correction Circuit ……………………………………………44
4.11 Gain Error Correction Architecture ……………………………46
4.11.1 Comparator of Gain Error Correction Circuit …………49
4.11.2 Power and Cost analysis on Gain Error Correction
Circuit …………………………………………………57
4.13 Single-Ended Input to Differential Output Circuit Circuit …………57

CHAPTER 5 CONCLUSIONS AND SUGGESTIONS ……………60
5.1 Conclusions ……………………………………………………60
5.2 Suggestions for Future Work ……………………………………64

REFERENCES …………………………………………………………65

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