臺灣博碩士論文加值系統

在此篇論文的研究中，我們研究『對稱和非對稱閘極的溝槽結構與鰭式無接面式場效電晶體』，我們利用乾式蝕刻方式將主動層薄化去取代直接沉積一層薄膜主動層的傳統方式，此方式比起直接沉積薄主動層可以得到較大的晶粒與較少的晶界。我們用乾式蝕刻方式成功形成溝槽結構並同時定義通道厚度（TCH）和柵極長度（LG）而且容易應用到無接面式場效電晶體元件。
此元件展現出極佳的電性，此溝槽式主動層結構能同時定義出元件的通道厚度及有效閘極長度，且非常相容於無接面式電晶體的製程。 像是SS值為89mV/dec-1以及的開關特性（ION/ IOFF>106），這主要是因為元件夠薄使的閘極擁有很好的控制能力。另外此元件在短通道效應的抑制上展現出極佳的能力相較於非對稱閘極，經實測，其DIBL值近似為0mV/V。
在此篇研究中首先是專注在元件製程以及基礎元件特性分析，之後為了測試此元件在應用面的廣度，我們會對此元件進行多種可靠度分析。像是在高溫下此元件在電性上的劣化反應、在高壓下的崩潰反應以及熱載子對元件產生的劣化反應。

This study describes the fabrication of a trench junctionless field-effect transistor (trench JL-FET) and asymmetric gate trench junctionless field-effect transistor (AG trench JL-FET). This study uses the dry oxidation to form the ultra-thin channel instead of directly depositing the thin-film as the poly-Si channel in JL-FET and it could get larger grain size and less grain boundary than directly depositing the thin-film. The dry etching process is utilized firstly in the fabrication of trench JL-FET is used to form a trench and define the channel thickness (TCH) and the gate length (LG) simultaneously. The trench structure was successfully and easily integrated into the JL-FET device.
The sub-threshold swing (SS) is 89mV/decade, and the ION/IOFF current ratio up to 106 due to the excellent gate controllability and ultra-thin channel. The trench JL-FET have a low drain induced barrier lowering (DIBL~0mV/V), indicating greater suppression of the short channel effect than in asymmetric gate JL-FET.
Firstly, this work focuses on the device process and basic device characteristics analysis. Next, the reliability analysis of trench JL-FET include high temperature performance, breakdown mechanism and hot carrier stress are investigated in this the analysis.

中文摘要 I
English Abstract II
致謝 III
目錄 IV
圖目錄 V
第一章 緒論 1
1-1 Junctionless元件介绍 1
1-2 動機 11
1-3 基本參數 16
第二章 元件製造 19
第三章 結果與討論 20
第四章 結論 31
參考資料 32

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