臺灣博碩士論文加值系統

本論文提出一個低功率高共模拒斥比 (Common Mode Reject Ratio, CMRR)的人體心電訊號(electrocardiogram, ECG)量測系統之類比前端電路(Analog Front-End , AFE)。整體AFE電路包含第一級儀表放大器(Instrumentation Amplifier, IA)，放大接收到的ECG訊號，第二級為四階高通濾波器(High-Pass Filter, HPF)，濾除2mHz以下的ECG訊號。第三級為一階有限增益低通濾波器(Low-Pass Filter, LPF)，提供40dB增益並濾除300Hz以上的訊號。第四級為陷波濾波器(Notch Filter)，阻絕電源供應系統的60Hz雜訊干擾。
整體AFE電路中的儀表放大器採用微分差動式儀表放大器並加入了共模回授(Common Mode Feedback, CMFB)電路更進一步提升CMRR。
濾波器中所採用的放大器為常見主動電流鏡負載式差動放大器，且差動放大器的偏壓電流皆壓在300nA以下，以降低功率消耗。整體電路差模增益能在達到67dB以上，CMRR可達到170dB以上。
本論文所設計之AFE電路皆使用台積電(TSMC) SiGe 180nm BiCMOS製程技術進行模擬驗證，操作電壓 1.8V，總體消耗功率小於9µW。

The present study proposes an analog front-end (AFE) circuit used in electrocardiogram (ECG) monitoring devices to achieve low-power common-mode rejection ratio (CMRR). The overall AFE circuit comprises an instrumentation amplifier (IA) to amplify the received ECG signals in the first stage, a fourth-order high-pass filter (HPF) to exclude ECG signals below 2 mHz in the second stage, a finite-gain low-pass filter (LPF) to provide a 40 dB gain and filter out signals over 300 Hz in the third stage, and a notch filter to block the 60 Hz noise interferences generated by the power supply system in the fourth stage.
A differential-type IA was employed in the overall AFE circuit, which was combined with a common mode feedback (CMFB) circuit to further enhance CMRR.
For the filter, the researchers adopted the common differential amplifier that uses a current mirror circuit as an active load. Subsequently, the bias current for the differential amplifier was maintained at below 300 nA to reduce power consumption. The overall differential mode gain was boosted to over 67 dB, enabling the CMRR to achieve over 170 dB.
The AFE circuit designed in the present study was simulated and verified using the SiGe 180nm BiCMOS processing technology developed by the Taiwan Semiconductor Manufacturing Company (TSMC). The simulations were controlled at a voltage of 1.8 V, for an overall power consumption less than 9 µW.

口試委員會審定書 #
誌謝 i
中文摘要 ii
ABSTRACT iii
目錄 iv
圖目錄 vii
表目錄 xi
第 一 章 緒論 1
1.1 研究動機………………….. 1
1.2 文獻探討 3
1.2.1 儀表放大器 3
1.2.2 右腳驅動電路 4
1.2.3 交流耦合電路(AC-Coupling circuit) 6
1.3 論文架構 6
第 二 章 ECG量測系統簡介 8
2.1 心電訊號量測 8
2.2 電源共模雜訊干擾 11
2.3 電路中的雜訊 12
第 三 章 電路設計與實現 14
3.1 儀表放大器比較 15
3.1.1 傳統式儀表放大器 15
3.1.2 轉導儀表放大器 16
3.1.3 電流平衡式儀表放大器 17
3.1.4 微分差動式儀表放大器 18
3.1.5 微分差動儀表放大器加入CMFB 19
3.2 濾波器(Filter) 26
3.2.1 一階低通濾波器設計 28
3.2.2 四階高通濾波器 31
3.2.3 帶斥濾波器(Band Reject Filter) 33
3.2.4 雙T型帶斥濾波器 34
3.3 類比前端放大電路所需要規格 36
3.4 放大器設計 37
第 四 章 模擬結果 42
4.1 儀表放大器模擬結果: 42
4.2 放大器模擬結果: 48
4.3 整體電路模擬結果: 53
第 五 章 結論 63
REFERENCE 64

[1]翁嘉英、林庭光、陳志暐、林俊龍、張宏儒(民104)。心理社會危險因子與心血管疾病。佛教慈濟醫療財團法人大林慈濟醫院心臟內科內科學誌。
[2]戴毓廷(民98)。生理訊號擷取系統設計概論。財人法團國家實驗研究院晶片系統設計中心電子報，7，3-5。
[3]陳旻毅(民100)。一個低功率低雜訊可攜式的類比前端心電訊號量測系統(碩士論文)。取自台灣碩博士論文系統。(系統編號 100NCTU5428110 )
[4]彰化基督教醫院心臟血管內科。簡易心電圖判別。[online]
www2.cch.org.tw/intern/ugy%20lecture/medical/EKG.pdf
[5]K. A. Ng and P. K. Chan, “A CMOS Analog Front-End IC for Portable EEG/ECG Monitoring Applications,” IEEE Trans. Circuit Syst. I: Regular papers, Vol. 52, no. 11, 2005.
[6]R. J. Baker, CMOS Circuit Design, Layout, and Simulation (3rd ed.). New York: Wiley, 2010.
[7]黃昭呈(民98)。應用於可攜式生醫訊號感測系統之低功率類比前端放大電路(碩士論文)。取自台灣碩博士論文系統。(系統編號 097NCKU5442081 )
[8]元智大學最佳化實驗室(民91)。主動式濾波器簡介。桃園市:吳明周。
[9]W. Allen, Active Filter Design, Boston, McGraw-Hill, 1991.
[10]B. Razavi, Design of Analog Integrated Circuit. Boston, McGraw-Hill, 2001.
[11]P.E. Allen and D. R. Holberg, CMOS Analog Circuit Design (2nd ed.), OxFord University Press, 2002.
[12]T. Chan Carusone, D.A. Johns and K. W. Martin, Analog Integrated Circuit Design (2nd ed), New York: Wiley, 2012.
[13]張文清(民102)。SPICE電子電路模擬。台北市:鼎茂圖書。
[14]鍾文耀、鄭美珠(民99)。CMOS電路模擬與設計:使用HSPICE (第三版)。台北縣:全華圖書。
[15]R. R. Harrison, “A low-Power Low-Noise CMOS Amplifier for Neural Recording Applications,” IEEE J. Solid-State Circuit, vol. 38, no. 6, 2003.
[16]J. D. Devi and P. V. Ramakrishna, “Design of CMOS Instrumentation Amplifier Using gm/ID Methodology,” Proc. Int. Conf. Circuit, cont. Comp., pp. 29‐32, 2014.
[17]T. V. Can, D. T. Wisland, T.S. Lande and F. Moradi, “Rail-to-Rail Low-Power Fully Differential OTA Utilizing Adaptive Biasing and Partial Feedback,” IEEE Nanoelectronics Group, Dep. Inf., 2010.
[18]G. Ferri, V. Stornelli and A. Celeste, “Integrated Rail-to-Rail Low-Voltage Low-Power Enhanced DC-Gain Fully Differential OTA,” ETRI Journal, vol. 29, pp. 785- 793, 2007.
[19]H. Alzaher and M. Ismail, “A CMOS Fully Balanced Differential Difference Amplifier and Its Applications,” IEEE Trans. Circuit Syst. II: Analog and Digital Signal processing, vol. 48, no. 6, 2001.
[20]B. B. Winter and J. G. Webster, “Driven-Right-Leg Circuit Design,” IEEE Trans. on Biomedical Engineering, vol. BME-30, pp. 62-66, 1983.
[21]E. M. Spinelli, R. Palles-Areny, and M. A. Mayosky, “AC-Coupled front-end for biopotential measurements,” IEEE Trans. on Biomedical Engineering, vol. 50 pp. 391-395, 2003.
[22]R. F. Yazicioglu, C. V. Hoof, and R. Puers, Biopotential Readout Circuit for Portable Acquisition Systems, 2008.
[23]P. A. Dal Fabbro, and C. A. dos Reis Filho, “An Integrated CMOS Instrumentation Amplifier with Improved CMRR,” IEEE Conf. Circuit and System Design, pp. 57-62, 2002.