臺灣博碩士論文加值系統

為了滿足深次微米技術的需求，互補式金氧半場效電晶體元件的縮小化必須包含著一些製程上的調整，其中最具挑戰的部分即是淺接面的研製。低能量的離子植入，搭配著低熱預算的回火製程，可以研製出更淺的接面。為了採用低熱預算的方案，我們運用低溫長時間的爐管回火及快速熱退火裝置來活化植入的雜質並且讓雜質無顯著的擴散現象發生。
此外，本文利用各種不同的低熱預算方案來執行淺接面的研製。第一種方案是在低溫下的爐管回火，第二種方案是在低溫下的爐管回火後隨即執行快速熱退火方式，第三種方案是先執行快速熱退火後再進行低溫下的爐管回火。第四種方案是在低溫下的爐管回火後隨即執行高溫下的爐管回火方式。在本文中，一併探討由不同技術所研製之接面，其雜質活化情形和漏電特性。

The scaling of CMOS devices to satisfy deep submicrometer technology requirements involves several process adjustments . One of the main challenges is the formation of shallow junction . Low-energy ion implantation , in tandem with low-thermal budget annealing processes , allows us to form shallower junctions . To adopt a low thermal budget scheme , we employed long-time low-temperature furnace annealing and rapid thermal annealing（RTA）as an approach of activating the implanted dopants without significant diffusion and eliminating the implanted-induced defects .
Moreover , various low thermal budget schemes have been performed to form shallow junctions . The first scheme is the low temperature furnace annealing . The second scheme is the low temperature furnace annealing followed by RTA . The third scheme is the RTA followed by low temperature furnace annealing . The fourth scheme is the low temperature furnace annealing followed by high temperature furnace annealing . In this thesis , the dopant activation and the electrical characteristics of junctions have also been investigated .

Abstract（in Chinese）……………………………………………………………………....Ⅰ
Abstract（in English）……………………………………………………………………….Ⅱ
Acknowledgements…………………………………………………………………………...Ⅲ
Contents………………………………………………………………………………………Ⅳ
Table Lists…………………………………………………………………………………….Ⅵ
Figure Captions……………………………………………………………………………….Ⅶ
Chapter 1. Introduction………………………………………………………………………....1
1.1 Motivation………………………………………………………………………………….1
1.2 Thesis Outline……………………………………………………………………………...4
Chapter 2. Experimental Procedures………………………………………………………..........5
2.1 Formation of Non-Silicided Shallow p+/n Junctions…………………………………….........5
2.2 Formation of Cobalt Silicided Shallow p+/n Junctions……………………………………......6
2.3 Formation of Non-Silicided Shallow n+/p Junctions……………………………………….....7
2.4 Formation of Cobalt Silicided Shallow n+/p Junctions…………………………………….......8
Chapter 3. Results and Discussions of p＋/n Junctions……………………………………...........10
3.1 Conventional High Temperature Furnace Annealing（HT）……………………………….....10
3.2 Low Temperature Furnace Annealing Scheme（LT）…………………………………….......11
3.3 Low Temperature Furnace Annealing followed by RTA Scheme（LT＋RTA）………….........13
3.4 Low Temperature Furnace Annealing followed by HT Furnace Annealing Scheme……...............15
3.5 RTA followed by Low Temperature Furnace Annealing Scheme（RTA＋LT）………….........15
Chapter 4. Results and Discussions of n＋/p Junctions…………………………………….............17
4.1 Conventional High Temperature Furnace Annealing（HT）……………………………….......17
4.2 Low Temperature Furnace Annealing Scheme（LT）……………………………………........18
4.3 RTA followed by Low Temperature Furnace Annealing Scheme（RTA＋LT）…………..........19
4.4 Low Temperature Furnace Annealing followed by HT Furnace Annealing Scheme……................20
Chapter 5. Conclusions……………………………………………………………………...........21
5.1 Conclusions of p＋/n Junctions……………………………………………………………....21
5.2 Conclusions of n＋/p Junctions……………………………………………………………....22
References……………………………………………………………………………………....23
Vita

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