臺灣博碩士論文加值系統

本論文提出一個適用於FlexRay車載網路通訊系統實體層之電路研究與設計，以因應未來汽車電子產品的蓬勃發展。為了使得各個電子產品能有效率的連結，降低連接線的數目與重量，車載網路的重要性與日遽增，而FlexRay網路通訊協定則能提供目前日益複雜的車載網路一個較佳的解決方案。
首先本論文主要提出一個類似於低電壓差動訊號的傳送電路架構，用以驅動FlexRay車載網路之雙絞線匯流排。而在接收電路的設計部分，提出了一個使用三個比較器的電路架構，用以接收與辨識雙絞線匯流排上資料與狀態間的變化。在製程選擇的考量上，使用了標準的0.18 μm CMOS邏輯製程，不僅能夠與其他的數位控制電路加以整合，亦不會使用到所費不貲的特殊高壓製程。
此外，在任何的控制系統設計中，穩定的時脈訊號是一個相當重要的控制要素，尤其是對於穩定性以及安全性要求極高的車用電子而言。在FlexRay系統中，每個節點間的時脈都是彼此獨立的，雖然FlexRay通訊協定能夠對時脈訊號進行同步校正，但因為FlexRay的通訊是建立在分時多工存取機制的基礎上，時脈的飄移則不能過大，所以本論文提出了一個能夠具有對抗製程、電壓、與溫度飄移的20 MHz時脈產生電路以及一個用來提供給FlexRay車載網路系統使用的低抖動80 MHz的頻率鎖相迴路，藉以降低外部環境所造成對於時脈訊號間的影響，使得提高整體車用電子系統的穩定性。
最後，因為車用電池除了供應車內電子設備之電源以外，另一個主要功能為啟動馬達用以發動汽車，期間瞬間電流與電壓變化則相當劇烈。所以本論文提出一個允許\高電壓輸入的直流切換式降壓轉換器，用來抵抗車用電子惡劣的環境因素。本論文提出利用堆疊式功率電晶體的架構、電壓轉換電路與相關偵測及控制電路，可在不需特殊高壓製程的情況下，允許\輸入電壓最高可達三倍電源電壓，且具有相當高的轉換效率以延長電源的使用時間，並易於整合於系統級晶片中，提供多準位的供應電壓源。

In this dissertation, we propose a circuit design and implementation of physical layer for FlexRay-based automotive communication systems which are expected to be widely used in car electronics for the years to come. To reduce the volume of electrical lines in a car and ensure safe connections, the automotive communication systems are more important than ever. FlexRay systems have been deemed as better than other existing solutions for the complicated in-vehicle networks.
A low-voltage differential-signaling-like transmitter is proposed to drive the twisted pair of the FlexRay bus. Furthermore, a three-comparator scheme is used to carry out bit slicing and state recognition at the receiver end. A prototype system as well as a chip implemented by using a typical 0.18 μm single-poly six-metal CMOS process is reported in this dissertation.
Furthermore, an accurate clock signal is required in any control system, especially in the vehicle applications, where the “safety” is the top priority. Because of the TDMA strategy (Time Division Multiple Access) was chosen for the FlexRay communication protocol, the system clock should not be drifting too much. A robust 20 MHz clock generator with process, supply voltage, and temperature compensation and a low-jitter 80 MHz phase-lock loop are proposed in this dissertation to reduce hostile environment effects.
Finally, because the “safety” and “reliability” are top design requirements in the automobile electronics, we should also focus on the power supply design in the in-car communication networks. Therefore, a high tolerant and high efficiency voltage converter is proposed in this dissertation. By utilizing stacked power MOSFETs, a voltage level converter, a detector and a controller, this design is realized by a typical CMOS process without any thick-oxide device to tolerate input voltage range up to 3 times of the VDD voltage.

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
1 Introduction 1
1.1 Background and motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Literature review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.1 The physical layer design of FlexRay systems . . . . . . . . . . . . . . 7
1.2.2 Low-jitter phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.3 High-Efficiency DC-DC Buck Converter . . . . . . . . . . . . . . . . . 9
1.3 Organization of this dissertation . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Transceiver Frontend Design of FlexRay Systems 13
2.1 Transceiver frontend design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.1 Transmitter (Tx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.2 Receiver (Rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.3 Design of the voltage regulator . . . . . . . . . . . . . . . . . . . . . . 19
2.2 20 MHz clock generator with PVT compensation . . . . . . . . . . . . . . . . 20
2.2.1 Differential ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.2 Replica bias circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.3 Process and temperature compensation circuit . . . . . . . . . . . . . . 23
2.2.4 Differential-to-single converter . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Implementation and measurement . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3 A Low-jitter 80 MHz PLL Design 34
3.1 Low-jitter PLL architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.1.1 Phase-frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . 35
3.1.2 Zero offset charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.3 Voltage-controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . 37
3.1.4 Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2 Implementation and measurement . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4 A High-Efficiency DC-DC Buck Converter for Sub-3×VDD Power Supply 43
4.1 Analysis of DC-DC buck converter . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1.1 Definition of indices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1.2 Efficiency analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2 The high-efficiency DC-DC buck converter design . . . . . . . . . . . . . . . . 44
4.2.1 The gate-oxide reliability . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2.2 Design of pulse-width modulator . . . . . . . . . . . . . . . . . . . . . 46
4.2.3 Design of internal reference voltage . . . . . . . . . . . . . . . . . . . . 50
4.2.4 Selection of off-chip passive components . . . . . . . . . . . . . . . . . 51
4.2.5 Design of error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.2.6 Stability analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.3 Implementation and measurement . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5 Conclusion and Future Works 60
5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.2 Future works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Bibliography 62

[1] Topology Research Institute. (2010, May). Analysis ofWorldwide Automotive MCU Manufacturers. [Online]. Available: http://www.topology.com.tw/
[2] K. Parnell, (2003, Aug.). Put the Right Bus in Your Car. [online]. Available: http://www.xilinx.com/
[3] CAN in Automation organization. (1999, Jul.). Controller Area Network. [Online]. Available: http://www.can-cia.org/
[4] LIN Consortium. (2003, Sep.). LIN Specification Package, Revision 2.0. [Online]. Available: http://www.lin subbus.org/
[5] MOST Cooperation. (2008, May). MOST Specification Revision 3.0. [Online]. Available: http://www.mostnet.de/
[6] H. Schopp and D. Teichner, “Video and audio applications in vehicles enabled by networked systems,” in Proc. Int. Conf. Consum. Electron., June 1999, pp. 218-219.
[7] FlexRay Consortium. (2006, Nov.). FlexRay Communication System Electrical Physical Layer Specification Version 2.1 Revision B. [Online]. Available: http//www.flexray.com/
[8] FlexRay Consortium. (2005, Dec.). FlexRay Communication System Protocol Specification Version 2.1 Revision A. [Online]. Available: http//www.flexray.com/
[9] Class B Data Communications Network Interface, SAE J1850 Standard, Jun. 2006.
[10] F. Herzel and B. Razavi, “A study of oscillator jitter due to supply and substrate noise,” IEEE Trans. Circuits and Syst. II, Analog Digit. Signal Process., vol. 46, no. 1, pp. 56-62, Jan. 1999.
[11] F. Baronti, P. D’Abramo, M. Knaipp, R. Minixhofer, R. Roncella, R. Saletti, M. Schrems, R. Serventi and V. Vescoli, “FlexRay transceiver in a 0.35um CMOS high-voltage technology,” in Proc. Design, Automation and Test in Europe, Mar. 2006, vol. 2, no. 6-10, pp. 1-5.
[12] F. Baronti, S. Saponara, E. Petri, R. Roncella, R. Saletti, L. Fanucci, and P. D’Abramo, “Hardware building blocks for high data-rate fault-tolerant in-vehicle networking,” in Proc. IEEE Int. Symp. Ind. Electron., Jun. 2007, pp. 89-94.
[13] C. Muller, M. Valle, R. Buzas, and A. Skoupy, “Mixed-mode behavioral model of flexray physical layer transceiver,” in Proc. European Conf. Circuit Theory and Design, Aug. 2009, pp. 527-530.
[14] P. M. Szecowka, and M. A. Swiderski, “On hardware implementation of Flexray bus guardian module,” in Proc. 14th Int. Conf. Mixed Design Integrated Circuits and Syst., Jun. 2007, pp. 309-312.
[15] M. Ei-Hage and F. Yuan, “An overview of low-voltage VCO delay cells and a worst-case analysis of supply noise sensitivity,” in Proc. Canadian Conf. Elect. and Comput. Eng., May 2004, vol. 3, pp. 1785-1788.
[16] J. M. Ingino and V. R. von Kaenel, “A 4-GHz clock system for a high-performance system-on-a-chip design,” IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 693-1698, Nov. 2001.
[17] J. G. Maneatis, “Low-jitter and process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
[18] X. Fan, C. Mishra, and E. Sanchez-Sinencio, “Signal Miller capacitor frequency compensation technique for low-power multistage amplifiers,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 584-592, Mar. 2005.
[19] H. W. Whittington, B. W. Flynn, and D. E. Macpherson, Switched Mode Power Supplies: Design and Construction, Hoboken, NJ: John Wiley & Sons, 1992.
[20] G. A. Rincon-Mora and P. E. Allen, “A low-voltage, low quiescent current, low drop-out regulator,” IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 36-44, Jan. 1998.
[21] L. Chen, B. Shi, and C. Lu, “Design and test of a synchronous PWM switching regulator system,” in Proc. IEEE APCCAS, Dec. 2000, pp. 517-520.
[22] R. W. Erickson, “DC-DC Power Converters,” article in Wiley Encyclopedia of Electrical and Electronics Engineering, 2008.
[23] T.-Y. Yu, “A high-efficiency synchronous CMOS switching regulator with PWM/PFM mode operation,” M.S. thesis, Dept. Elect. Eng., National Chiao Tung Univ., Taiwan, 2003.
[24] C.-C. Wang, C.-L. Lee, C.-Y. Hsiao, and J.-F. Huang, “Clock recovery and data recovery design for LVDS transceiver used in LCD panels,” in Proc. IEEE APCCAS, Dec. 2004, vol. 2, p.861-864.
[25] C.-C. Wang and J.-M. Huang, “1.0 Gbps LVDS transceiver design using a common mode DC biasing,” in Proc. 15th VLSI Design/CAD Symp., Aug. 2004, pp. 14.
[26] R. F. Pierret, Semiconductor Device Fundamentals, Reading, MA: Addison-Wesley, 1996.
[27] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 2nd ed., London, U.K.: Oxford Univ. Press, 2002.
[28] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, and Simulation, Piscataway, NJ: IEEE Press, 1998.
[29] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, Nov. 1996.
[30] K. Sundaresan, P. E. Allen, F. Ayazi, “Process and temperature compensation in a 7-MHz CMOS clock oscillator,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 433-442, Feb. 2006.
[31] C.-C. Wang, G.-N. Sung, and P.-C. Chen, “A transceiver design for electronic control unit (ECU) nodes in FlexRay-based automotive communication systems,” in Proc. Int. Conf. Consum. Electron., Jan. 2008, pp. 1-2.
[32] N. Navet, Y. Song, F. Simonot-Lion, and C. Wilwert, “Trends in automotive communication Systems,” Proc. IEEE, vol. 93, no. 6, pp. 1204-1223, June 2005.
[33] S. Srivastava and J. Roychowdhury, “Analytical equations for nonlinear phase errors and jitter in ring oscillators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 10, pp. 2321-2329, Oct. 2007.
[34] W. Liu, X. Jin, J. Chen, M.-C. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P. K. Ko, and C. Hu, BSIM 3.3.2 User''s Manual, Berkeley, CA: Univ. California, 1999.
[35] NXP Semiconductors. (Jul. 2007). TJA1080, FlexRay Transceiver.
[36] H. Heinecke, “Automotive system design - challenges and potential,” in Proc Design, Automation and Test in Europe, vol. 1, pp. 656-657, March 2005.
[37] J. Lee, and B. Kim, “A 250MHz low jitter adaptive bandwidth PLL,” in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., Feb. 1999, pp. 346-347.
[38] C. Kim, I. Hwang, and S. Kang “A lower-power small-area ±7.28-ps-Jitter 1 GHz DLLBased clock generator,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1414-1420, Nov. 2002.
[39] B.W. Garlepp, K. S. Donnelly, J. Kim, P. S. Chau, J. L. Zerbe, C. Huang, C. V. Tran, C. L. Portmann, D. Stark, Y.-F. Chan, T. H. Lee, and M. A. Horowitz, “A portable digital DLL for high-speed CMOS interface circuits,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 632-644, May 1999.
[40] J.-B. Lee, K.-H. Kim, C. Yoo, S. Lee, O.-G. Na, C.-Y. Lee, H.-Y. Song, J.-S. Lee, Z.-H. Lee, K.-W. Yeom, H.-J. Chung, I.-W. Seo, M.-S. Chae, Y.-H. Choi, and S.-I. Cho,
“Digitally-controlled DLL and I/O circuits for 500 Mb/s/pin x DDR SDRAM,” in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., Feb. 2001, pp. 68-69.
[41] W. B. David, “A Low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 513-519, Apr. 1999.
[42] V. von Kaenel, D. Aebischer, R. van Dongen, and C. Piguet, “A 600 MHz CMOS PLL microprocessor clock generator in Dig. Tech. Papers IEEE Int. Solid-State Circuits Conf., Feb. 1998, pp. 396-397.
[43] R. E. Best, Phase-Locked Loops: Design, Simulation, and Application, Columbus, OH: McGraw-Hill, 2003.
[44] P. Sotiriadis, “Timing and spectral properties of the Flying Adder frequency synthesizers,” in Proc. IEEE Int. Frequency Control Symp., Jul. 2009, pp. 788-792.
[45] H. Mair and L. Xiu, “An architecture of high-performance frequency and phase synthesis,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 835-846, Jun. 2000.
[46] A. J. Stratakos, “High-efficiency low-voltage DC-DC conversion for portable applications,” M.S. thesis, Univ. California, Berkeley, California, 1998.
[47] B. Murari, F. Bertotti, and G.A. Vignola, Smart Power ICs, 2nd ed., New York, NY: Springer, 2002.
[48] Linear Technology Inc., (Oct. 1999.) LTC1772: Constant Frequency Current Mode Step-Down DC/DC Controller in SOT-23.
[49] J.F. da Rocha, M.B. dos Santos, J.M. Dores Costa, and F.A. Lima, “Level shifters and
DCVSL for a low-voltage CMOS 4.2-V buck converter,” IEEE Trans. Ind. Electron., vol. 55, no. 9, pp. 3315-3323, Sept. 2008.
[50] M. Siu, P. K. T. Mok, K. N. Leung, Y. H. Lam, and W. H. Ki, “A voltage-mode PWM buck regulator with end-point prediction,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 4, pp. 294-298, Apr. 2006.
[51] A. I. Pressman, K. Billings, and T. Morey, Switching Power Supply, 3rd ed., Columbus, OH: McGraw-Hill, 2009.
[52] M. Brown , Power Supply Cookbook, 2nd ed., Maryland, MO: Newnes, 2001.
[53] F. Luo, D. Ma, “Design of digital tri-mode adaptive-output buck-boost power converter for power-efficient integrated systems,” IEEE Trans. Ind. Electron., vol. 57, no. 6, pp. 2151-2160, Jun. 2010.
[54] J. Jr. Bongiorno and D. Graham, “An extension of the Nyquist-Barkhausen stability criterion to linear lumped-parameter systems with time-varying elements,” IEEE Trans. Autom. Control, vol. 8, no. 2, pp. 166-170, Apr. 1963.
[55] Sipex Corp. (2006, Dec.). Selecting Appropriate Compensation: Type-II or Type-III. [Online]. Avaliable: http://www.exar.com/Files/Documents/sipex/ApplicationNotes/ANP-18 SelectTypeIIorTypeIII 120506.pdf
[56] J. Xiao, A. Peterchev, J. Zhang, and S. Sanders, “An ultra-low-power digitally-controlled buck converter IC for cellular phone applications,” in Proc. IEEE Applied Power Electron. Conf. and Exposition, Feb. 2004, vol. 1, pp. 383-391.
[57] C.-C. Chang, “A high-efficiency CMOS DC-DC converter with a new active current sensor for portable applications,” M.S. Thesis, Dept. Elect. Eng., Yuan Ze Univ., Taiwan, 2005.
[58] F.-F. Ma, “Advanced control and protection techniques for DC-DC switched mode power supply IC design,” Ph.D. Dissertation, Dept. Elect. Eng., National Chiao Tung Univ., Taiwan, 2006.