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研究生:蘇文鴻
研究生(外文):Wen-Hong Su
論文名稱:數位影像處理之類比前端電路設計
論文名稱(外文):Analog Front-End Circuit Design for Digital Image Processing
指導教授:杜弘隆
指導教授(外文):Steve Hung-Lung Tu
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:98
語文別:中文
論文頁數:70
中文關鍵詞:數位影像處理高解析度消費性解析度事務機設計類
外文關鍵詞:PPSAPSCCDdynamicdesign
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隨著數位相機的日漸普及,人人隨手一台就可以紀綠影像及聲音,加上多功能事務機的出現,更讓一般掃描文件變得簡單。影像處理IC已經和社會大眾所能接受的消費性電子產品密不可分。在設計影像處理IC的核心電路,一直以來都是由二大架構在彼此競爭,一是由標準的CMOS架構所組成,而另外一種是由CCD架構所組成。

目前此二大架構之產品應該主要是以價格及解析度來做為區分。因為CCD架構的影像處理IC,具有S/N佳及動態範圍大之優點,所以主要是被應用在高解析度及快掃描速度為主之影像產品。反之,CMOS架構之影像處理IC,因S/N不如CCD架構且由於電路所包含之offset需要做處理,所以被應用在低解析度及掃描速度慢之產品。

本論文是針對CMOS影像IC在設計類比前端讀取電路時,需考慮的設計規格而提出一種不同於一般傳統CMOS類比前端讀取電路之架構來克服S/N不如CCD架構之問題,進而使此架構能被應用在更高解析度及快掃描速度上。
With the proliferation of digital cameras and multi-functional printers, document scanning has become much more easily. Image processor IC’s have been popular consumer electronic products. The core image processor IC’s can be classified two catalogs: one is based on CMOS technologies and the other is with CCD architecture.

The two factors, price and resolution actually determine the applications of the two image processor IC’s. The CCD based image IC’s have the advantages of high S/N and large dynamic range, which therefore are employed in the products of high resolution and high scan speed. By contract, CMOS based image IC’s are used in low-resolution and low-speed products.

In this thesis, we present the analog front-end readout circuit design specifications of CMOS image IC’s. Meanwhile, we also propose a novel architecture of the readout circuits to improve the S/N of CMOS based image IC’s, which we expect the proposed architecture can be applied in high-resolution and high-speed image circuits.
頁次
摘要 i
英文摘要 ii
誌謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
第一章 前 言 1
第二章 影像感測架構及動作原理 3
2.1 光感測器的介紹及應用 3
2.2 CCD and CMOS在影像感測上的應用 5
2.3 CCD影像感測器的動作原理和分析 7
2.4 CMOS影像感測器的動作原理和分析 10
第三章 影像讀取電路之設計 18
3.1光二極體和光電晶體 18
3.2 FPN和CDS電路 22
3.3輸出飽合電壓和S/N比 25
3.4一維APS架構的CMOS影像感測器及時序圖 27
3.5一維PPS架構的CMOS影像感測器及時序圖 29
3.6改良後一維PPS架構的CMOS影像感測器及時序圖 32
第四章 CMOS影像讀取電路之晶片實作 35
4.1 APS電路和光二極體感測元件 35
4.2新型式PPS電路和光電晶體感測元件 38
4.3 模擬結果比較 41
4.4 晶片量測結果與分析 47
第五章 結果討論與未來發展 54
參考文獻 55
附錄A 56
附錄B 57
附錄C 所投稿之paper 58
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[10]Iliana L. Fujimori, Ching-Chun Wang, and Charles G. Sodini, Fellow, “A 256 ×256 CMOS differential passive pixel imager with FPN reduction techniques,” IEEE JSSC, vol. 35, no. 12, Dec. 2000.
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[13]米本和也原著,陳榕庭、彭美桂譯,CCD/CMOS影像感測器之基礎與應用, Oct. 2005.
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