臺灣博碩士論文加值系統

論文中針對可調式分數延遲數位濾波器進行了三種型式（有限脈衝響應、全通、無限脈衝響應）的設計，使用權重式最小平方差概念設計濾波器的誤差函數，並在實現系統的過程中引入菲蘿結構。硬體設計中，使用移位法處理含小數點的數字運算，避免使用浮點元件必然會帶來的高電路複雜度。硬體電路以Verilog硬體描述語言設計，並於ModelSim（Mentor Graphics公司發行之硬體描述語言程式設計工具）中進行驗證，硬體波型圖最終將與理論設計所得之運算結果相比較。各硬體設計經過Design Vision（Synopsys公司發行之數位邏輯合成工具）合成後的結構圖放置在各章結尾處，而它們的面積、時脈、功率報告則置於附錄中。

In the thesis, three types (finite impulse response, allpass, and infinite impulse response) of design on variable fractional-delay filters are proposed, and the technique of weighted-least-square method will be applied. For the implementation of the designed system, Farrow structure will be incorporated in the design of the stated variable fractional-delay filters. In the hardware design, shifting method takes the place of floating-point unit in order to decrease the complexity of circuits. The　circuits are designed in Verilog harware description language with ModelSim. After making sure the fuctions are correct, we compare waveforms with the outcomes of theoretical computation. The schematics after synthesizing from Design Vision are showed in the end of each chapter. Area reports, timing reports, and power reports will be found in the appendix.

誌謝 i
摘要 ii
ABSTRACT iii
目錄 iv
圖目錄 vi
表目錄 ix
第１章 序論 1
1.1　　研究背景與動機 1
1.2　　基礎概念與研究目標 2
1.2.1　次方多項式與Farrow Structure 2
1.2.2　FIR系統 2
1.2.3　Allpass系統 3
1.2.4　IIR系統 4
1.2.5　WLS方法 5
1.3　　論文組織 5
第２章 可調式分數延遲FIR數位濾波器之設計與實現 7
2.1　　設計可調式分數延遲FIR數位濾波器 7
2.1.1　混合Farrow Structure的可調式分數延遲FIR數位濾波器結構 7
2.1.2　係數對稱性 8
2.1.3　可調式分數延遲FIR數位濾波器的誤差函數 10
2.1.4　可調式分數延遲FIR數位濾波器的設計係數 12
2.1.5　可調式分數延遲FIR數位濾波器之係數設計範例 14
2.2　　實現可調式分數延遲FIR數位濾波器 17
2.2.1　可調式分數延遲FIR數位濾波器的系統結構 17
2.2.2　可調式分數延遲FIR數位濾波器的硬體結構分析 19
2.2.3　可調式分數延遲FIR數位濾波器的硬體運作結果與分析 22
2.2.4　可調式分數延遲FIR數位濾波器的硬體合成結果 44
第３章 可調式分數延遲Allpass數位濾波器之設計與實現 45
3.1　　設計可調式分數延遲Allpass數位濾波器 45
3.1.1　混合Farrow Structure的可調式分數延遲Allpass數位濾波器結構 45
3.1.2　相位逼近 46
3.1.3　可調式分數延遲Allpass數位濾波器的誤差函數 48
3.1.4　可調式分數延遲Allpass數位濾波器的設計係數 49
3.1.5　可調式分數延遲Allpass數位濾波器之係數設計範例 50
3.2　　實現可調式分數延遲Allpass數位濾波器 54
3.2.1　可調式分數延遲Allpass數位濾波器的系統結構 54
3.2.2　可調式分數延遲Allpass數位濾波器的硬體結構分析 56
3.2.3　可調式分數延遲Allpass數位濾波器的硬體運作結果與分析 59
3.2.4　可調式分數延遲Allpass數位濾波器的硬體合成結果 82
第４章 可調式分數延遲IIR數位濾波器之設計與實現 83
4.1　　設計可調式分數延遲IIR數位濾波器 83
4.1.1　混合Farrow Structure的可調式分數延遲IIR數位濾波器結構 83
4.1.2　振幅響應趨近 84
4.1.3　穩定條件函數 86
4.1.4　可調式分數延遲IIR數位濾波器的誤差函數與設計係數 87
4.1.5　可調式分數延遲IIR數位濾波器之係數設計範例 89
4.2　　實現可調式分數延遲IIR數位濾波器 93
4.2.1　可調式分數延遲IIR數位濾波器的系統結構 93
4.2.2　可調式分數延遲IIR數位濾波器的硬體結構分析 94
4.2.3　可調式分數延遲IIR數位濾波器的硬體運作結果與分析 98
4.2.4　可調式分數延遲IIR數位濾波器的硬體合成結果 121
第５章 結論與未來展望 123
5.1　　結論 123
5.2　　未來展望 124
參考文獻 125
附錄 129
A.1　　可調式分數延遲FIR數位濾波器的合成報告 129
A.1.1　可調式分數延遲FIR數位濾波器的硬體Area Report 129
A.1.2　可調式分數延遲FIR數位濾波器的硬體Timing Report 129
A.1.3　可調式分數延遲FIR數位濾波器的硬體Power Report 130
A.2　　可調式分數延遲Allpass數位濾波器的合成報告 131
A.2.1　可調式分數延遲Allpass數位濾波器的硬體Area Report 131
A.2.2　可調式分數延遲Allpass數位濾波器的硬體Timing Report 131
A.2.3　可調式分數延遲Allpass數位濾波器的硬體Power Report 132
A.3　　可調式分數延遲IIR數位濾波器的合成報告 133
A.3.1　可調式分數延遲IIR數位濾波器的硬體Area Report 133
A.3.2　可調式分數延遲IIR數位濾波器的硬體Timing Report 133
A.3.3　可調式分數延遲IIR數位濾波器的硬體Power Report 134

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