臺灣博碩士論文加值系統

本論文為提出一縮小型CMOS耦合器設計，係利用變壓器模型以及補償電容有效的縮小電路尺寸並抵抗因板材損耗所造成之相位誤差。接著更進一步利用可變電容取代固定式電容使耦合器具有可重置之機制，達到頻率可調的目標。
本設計之縮小型耦合器是以集總元件實現來達到縮小化之目的，其操作頻段分別設計在900 MHz以及4 GHz，電路尺寸分別為0.53×0.26 mm2和0.37×0.38 mm2，具有小型化之特性。且由於補償電容的架構使本設計之耦合器亦具有精準之輸出相位差。接著，具可重置機制之耦合器其設計頻段於4 GHz，分別設計具有33 % (3.8∼5.2 GHz)可調頻寬以及44 % (3.7 GHz∼5.85 GHz)可調頻寬之耦合器。在可調頻段內，其輸出相位差誤差值分別為91°±1°和90°±2.5°。
利用縮小型耦合器設計，本論文將其應用於巴特勒矩陣中，提出一新式4×4 CMOS巴特勒矩陣設計，其操作頻率為2.45 GHz。此設計除了能產生傳統4×4巴特勒矩陣設計的四組相位分佈外，還可提供額外的兩組輸出相位，使後級陣列天線在透過本設計之巴特勒矩陣輸入訊號後能產生六組不同方向之波束。此外，本設計亦將前級單刀四擲開關整合到本設計晶片中，使本設計之巴特勒矩陣更容易與前級電路做整合。

In this thesis work, a miniaturized CMOS hybrid is studied and implemented in the related circuits. By using the transformer-based model and compensatory capacitor, the phase error caused by substrate loss can be compensated, and the chip size can be dramatically reduced.
The miniaturized hybrids, which are realized by lump elements using 0.18-

第一章 序論
1.1 研究動機
1.2 論文內容綱要
第二章 可調式耦合器設計原理
2.1 耦合器設計理論
2.1.1 集總化元件之耦合器設計原理
2.1.2 具相位補償之縮小型耦合器設計原理
2.2 可調頻帶耦合器設計原理
第三章 新型CMOS 4×4巴特勒矩陣設計
3.1 巴特勒矩陣介紹
3.2 晶片型巴特勒矩陣設計
3.3 新式晶片型巴特勒矩陣設計
3.3.1 90°耦合器設計
3.3.2 具可切換機制之45°/90°相移器
3.3.3 雙刀雙擲開關設計
3.3.4 單刀四擲開關設計
3.4 新式4×4巴特勒矩陣佈局與量測考量
3.5 晶片模擬結果
第四章 結論與未來展望
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