臺灣博碩士論文加值系統

近年來，隨著製程技術不斷的進步，使得快閃記憶體元件不斷的微縮，但平面元件微縮空間有限，因此要如何增加記憶體元件的密度以及提升操作特性是重要的議題。目前有許多解決方法被提出，如應用高介電常數材料、無接面快閃記憶體元件、多晶矽、環繞閘極結構和三維堆疊等等。本篇論文應用環繞閘極無接面快閃記憶體元件，利用在通道轉角之尖端電場增強效應，來改善操作特性，探討不同電荷捕捉層以及阻擋氧化層的元件操作特性。
首先，在奈米線與環繞閘極結構的穿隧氧化層是分別使用低溫感應耦合電漿氣相沉積(ICPCVD)，以及使用高溫快速熱退火成長，並且使用四氮化三矽/二氧化鉿作為電荷捕捉層。實驗結果得知，藉由環繞閘極結構與奈米線比較，較大的電場增強，使得寫入速度大幅提升。但在元件的可靠度，由於環繞閘極結構在上沉積穿隧氧化層時，使用的ICPCVD其通道覆蓋性不佳，使得耐久力變差。
第二部分，分別使用四氮化三矽/二氧化鉿以及四氮化三矽/二氧化鋯堆疊的電荷捕捉層分別是由高溫爐管以及原子層沉積技術沉積而成，而穿隧氧化層是由高溫急速升溫氧化形成。我們發現四氮化三矽/二氧化鋯的堆疊元件比四氮化三矽/二氧化鉿的抹除速度還快，而在氮化矽與二氧化鉿或二氧化鋯的中間加入三氧化二鋁，可改善電荷保持力以及耐久力的問題。
最後一部分，實驗採用不同阻擋氧化層的環繞閘極快閃記憶體元件並對元件的操作特性做分析。結果顯示具有或沒有堆疊阻擋層元件的寫入及抹除速度都差不多。在高溫量測的電荷保持力，才可看到元件特性的差別，電荷保持力可由堆疊多層的阻擋氧化層來改善。

In recent years, flash memory device can be continuously scaled down by continuous advance in process technology. However, the scale down of planar flash memory device can not be continued due to its limitation of shrinkage. How to increase the density of memory devices and enhance operating characteristics are important issues. Some approaches have been reported to solve these issues, such as high-k material, junctionless (JL) channel, poly-Si channel, nanowire (NW) structure, gate all around (GAA) structure and 3D stack devices. In this thesis, operation characteristics of flash memory GAA devices are improved by enhance electric field at channel cornors. Operation characteristics of GAA device with different charge trapping layers and blocking oxides layers are also studied.
In the first part, tunneling oxides of devices with NW and GAA structure are formed by low-temperature inductively coupled plasma chemical vapor deposition (ICPCVD) and high-temperature rapid thermal oxidation (RTO) and Si3N4/HfO2 trapping layers are applied. In this work, program speed of gate all around device is faster than that of NW one due to larger enhancement of electric field. Reliabilities of GAA decice are worse than that of NW one due to poor step coverage of tunneling oxide layers are formed by ICPCVD.
In the second part, Si3N4/HfO2 and Si3N4/ZrO2 stacked trapping layers are deposited by low-pressure chemical vapor deposition (LPCVD) and atomic layer deposition (ALD), and tunneling oxides are formed by RTO. Device with Si3N4/ZrO2 stacked trapping layers shows faster erasing speed are compared to that with Si3N4/HfO2 ones. Additional Al2O3 trapping layer are added between Si3N4 and HfO2 or ZrO2 layer. Results show that both retention and endurance are improved by the additional Al2O3 layer.
In the last part, effects of stacked blocking oxide layers on operation characteristics of GAA flash memory devices are investigated. Results show that programing and erasing speed of devices with or without stacked blocking layers are similar. Retention characteristics at high-temperature are improved by stacked blocking oxide layers.

摘要 i
Abstract ii
致謝 iv
目錄 vi
第一章 序論 1
1.1快閃記憶體元件 1
1.1.1 浮動閘極式快閃記憶體元件 1
1.1.2 電荷捕陷式快閃記憶體元件 2
1.2多晶矽薄膜電晶體 4
1.3多向式閘極結構與奈米線通道式快閃記憶體元件 5
1.3.1 多向式閘極結構 5
1.3.2 三維結構與奈米線通道 5
1.4高介電係數材料與能帶工程之介紹 6
1.4.1高介電係數材料 6
1.4.2能帶工程 7
1.4.3 不同高介電層材料的阻擋層之能帶工程電荷捕陷式快閃記憶體 8
1.5無接面快閃記憶體元件介紹 10
1.6三維結構可堆疊式NAND快閃記憶體 11
1.7各章摘要 13
第二章 快閃記憶體元件製程與操作方法 19
2.1快閃記憶體元件製程 19
2.1.1 傳統平面式快閃記憶體元件 19
2.1.2 奈米線式通道快閃記憶體元件製程 20
2.1.3 環繞式閘極通道快閃記憶體元件製程 20
2.2 快閃記憶體元件寫入與抹除方法 21
2.2.1 CHEI通道熱電子注入寫入 21
2.2.2 F-N穿隧寫入 22
2.2.3 F-N穿隧抹除 23
2.3 快閃記憶體元件可靠度特性 24
2.3.1 電荷保持力 24
2.3.2 耐久力 25
2.4閘極與汲極之干擾特性 26
第三章 利用高低溫成長二氧化矽的穿隧層於多晶矽無接面環繞閘極快閃記憶體之操作電性研究 37
3.1研究動機與背景 39
3.2實驗 40
3.3結果與討論 41
3.3.1元件汲極電流對閘極電壓圖與成分分析 41
3.3.2元件寫入與抹除特性 41
3.3.3元件可靠度特性 43
3.4結論 44
第四章 利用不同電荷捕捉層之能帶工程於多晶矽無接面環繞閘極快閃記憶體之操作電性研究 53
4.1研究動機與背景 54
4.2實驗 55
4.3結果與討論 55
4.3.1元件汲極電流對閘極電壓圖與成分分析 56
4.3.2元件寫入與抹除特性 56
4.3.3 元件可靠度特性 57
4.4結論 58
第五章 利用不同阻擋氧化層之能帶工程於多晶矽無接面環繞閘極元件快閃記憶體之特性研究 69
5.1研究動機與背景 70
5.2實驗 71
5.3結果與討論 72
5.3.1元件汲極電流對閘極電壓圖與成分分析 72
5.3.2元件寫入與抹除特性 72
5.3.3 元件可靠度特性 73
5.4結論 74
第六章 結論 91
參考文獻 94

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