臺灣博碩士論文加值系統

隨著技術的演進，低功率系統在可攜式消費性電子、生醫感測晶片及無線感測網路等應用上已成為趨勢。對於這些應用而言，主要有三個考量因素：系統建置成本、傳輸距離與電池壽命。裝置成本由元件數量與晶片面積所決定，外部元件越少、晶片面積越小就可以壓低裝置的價格；傳輸距離由傳輸機的輸出功率與接收機的靈敏度所決定。然而，越高的輸出功率與靈敏度也會使得裝置的功率消耗上升；電池壽命被裝置的功率消耗所限制，裝置功率消耗越大，越需要頻繁的更換電池。
本論文分別提出了一個低功耗的傳輸機以及低功耗接收機架構。首先，為了製作一個低功耗，但是高頻率穩定度的傳輸機，此晶片使用次載波注入鎖定鎖相迴路與電容耦合電路實現兩階段升頻技術。兩階段升頻技術可以解決傳統高階鎖相迴路所碰到的高功耗問題和雜訊問題。此晶片以TSMC 0.18μm CMOS製程製作，總晶片面積為2.23mm2。鎖相迴路輸出頻率為48MHz，相位雜訊為-95.42dBc/Hz @100kHz、-118.58dBc/Hz @1MHz。在0.8V電源供應下，系統功率消耗為248μW，輸出功率為-24dBm。
為了避免使用笨重的表面聲波濾波器與石英振盪器，但又希望能夠維持良好的靈敏度表現，接收機採用混頻器優先架構實現優異的頻率選擇度。除此之外，此晶片也透過頻率補償電路最佳化中頻的頻寬與LC振盪器的頻率，和利用斬波放大器過濾閃爍雜訊。此晶片以TSMC 0.18μm CMOS製程製作，總晶片面積為3.82mm2。在0.8V電源供應下，系統功率消耗為162μW，最高接收速率為30kbps。

Nowadays, with the development of silicon technology, the low-power system has become more and more popular in portable consumer electronics, bio-sensing systems, and internet-of-things applications. For these applications, there are three issues: the cost of the components, transmission distance, and battery life. The cost is determined with the number of the off-chip components and the size of each chip. The lower the number of the components and the chip size, the lower the price of the system; transmission distance is determined by the output power of the transmitter and the sensitivity of the receiver. To extend the distance, the output power and sensitivity should be higher, but this also causes an increase in power consumption; the system power consumption limits the battery life.
In the thesis, a low-power 433MHz transmitter and receiver are proposed. To implement a low-power but high-accuracy transmitter, the work adopts a two-step frequency multiplication technique with the subharmonically injection-locked PLL (SILPLL) and the capacitive coupling circuit. The two-step frequency multiplication technique alleviates the high-power and noise problems that conventional high-order PLL suffers and balances the power consumption and noise performance. The chip was fabricated in a 0.18μm CMOS process, and the chip area is 2.23mm2. The output frequency of the PLL is 48MHz, and the phase noise is -95.42dBc/Hz @100kHz and -118.58dBc/Hz @1MHz. The system power consumption and output power is 248μW and -24dBm under 0.8V supply voltage, respectively.
To obviate the requirement of the bulky SAW filter and crystal oscillator but still maintain high-sensitivity, the proposed low-power receiver adopts the mixer-first architecture to implement a high-Q channel selection, the frequency calibration path to optimized IF bandwidth and the VCO frequency, and the chopper amplifier to remove the effects of the flicker noise. The chip was fabricated with 0.18um CMOS process, and the chip area is 3.82mm2. The system power consumption and maximum data rate are 162μW and 30kbps under a 0.8V supply.

Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.1.1 Applications of the Wireless Sensor Networks 1
1.1.2 The Challenges of the Wireless Sensor Networks 1
1.1.3 Consideration of the Low-Power Wireless System 4
1.2 Review of the Low-Power Transmitters and Receivers 8
1.2.1 Design Considerations of the Low-power Transmitter 8
1.2.2 State-of-the-art Transmitters 9
1.2.3 Design Consideration of the Wake-up Receiver 11
1.2.4 State-of-the-art Wake-up Receivers 12
1.3 Thesis Purpose and Thesis Organization 16
Chapter 2 Low-Power Wireless Transmitter with Two-step Frequency Multiplication Technique to Reduce the Power Consumption 19
2.1 Proposed Transmitter Architecture 20
2.2 Design Consideration 21
2.2.1 The SILPLL 21
2.2.2 The Capacitive Coupling Circuit 24
2.3 Circuit Implementation 25
2.3.1 The SILPLL 25
2.3.2 The Class-E Power Amplifier 27
2.4 Simulation Results 28
2.4.1 Ring Oscillator 28
2.4.2 Injection-locked Function 28
2.4.3 Phase-locked Loop Function 30
2.4.4 Power Amplifier 36
2.5 Measurement Results 38
2.5.1 The SILPLL 38
2.5.2 The Power Amplifier 39
2.5.3 The Full System Characterization 40
2.5.4 Performance Summary and Comparison 41
2.6 Summary of the Proposed Wireless Transmitter 41
Chapter 3 Low-Power Wireless Receiver with a Frequency Calibration Loop 42
3.1 Proposed Receiver Architecture 42
3.2 Design Consideration 43
3.2.1 N-path Filter 43
3.3 Circuit Implementation 47
3.3.1 LC Oscillator and Start-up Circuit 47
3.3.2 IF Band Gain Path and Baseband Gain Path 48
3.3.3 Frequency Calibration Path 50
3.4 Simulation Results 53
3.4.1 N-path Filter 53
3.4.2 LC Oscillator 54
3.4.3 IF Band Gain Path and Baseband Gain Path 56
3.4.4 Frequency Calibration Path 58
3.5 Measurement Results 61
3.5.1 N-path Filter 61
3.5.2 LC Oscillator 62
3.5.3 IF Band Gain Path and Baseband Gain Path 63
3.5.4 Frequency Calibration Path 66
3.5.5 Comparison Table 68
3.6 Summary of the Proposed Wireless Receiver 69
Chapter 4 Conclusion and Future Work 70
Reference 72

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