臺灣博碩士論文加值系統

本論文提出三個直流-直流電壓轉換器，第一個轉換器為使用適應性導通時間控制式降壓轉換器，此控制電路分為兩個迴路路徑，一個為主要輸出電壓回授路徑，另一個為鎖相迴路，藉由包含適應性電路加快暫態反應時間，最後藉由鎖相迴路外接頻率鎖定切換頻率。晶片面積1.23042 x 1.24995 mm2，輸入電壓為3V到3.6V，輸出電壓為1V到2.6V，在負載電流為300mA時，最高效率為90.52%。
　　第二個轉換器為低雜訊連續時間三角積分升壓轉換器，它使用連續時間三角積分，解決輸出雜訊的影響，並加入一快速響應迴路，使其升壓轉換器能有較快的負載調節率。晶片面積為1.34142 x 1.440615 mm2，輸入電壓為0.9V到1.5V，輸出電壓為3.3V，在負載電流為50mA時，最高效率為89.57%。
第三個轉換器為新型主動式電感電流感測技術之磁滯電流控制降壓轉換器，此控制電路藉由產生上下限電流，使電感電流在一定區間做切換，加速暫態響應時間，並且採用新的電感電流感測電路，晶片面積為1.1605 x1.408325 mm2，輸入電壓為3V到3.6V，輸出電壓為1V到2.5V，最高效率為94.54%。
以上晶片皆採用台灣積體電路公司0.35-μm互補式金屬氧化物半導體製程來實現。

The thesis proposes three DC-DC converters. The first proposed converter is a ripple-based buck converter with phase-frequency-locked (PFL) and adaptive on-time (AOT) techniques. Its principal controlled loop contains an output voltage feedback path and a phase-frequency-locked path. The PFL loop comprises an AOT controller to accelerate the transient time and lock the switching frequency. The chip size is 1.538 mm2. The input voltage ranges between 3V and 3.6V and the output voltage ranges are between 1V and 2.6V. The peak efficiency is 90.52% at 300mA load current.
In order to reduce the output noise, the thesis proposes the second converter, a low-noise boost-converter using continuous-time (CT) delta-sigma technique with a fast transient path. The chip size is 1.932 mm2. Its input voltage ranges are from 0.9 V to 1.5 V and its output voltage is 3.3 V. The maximum efficiency is 89.57% at 50 mA load current.
The third proposed converter is a hysteresis-current-controlled buck converter with a new active inductor current sensing scheme. Its controlled circuit speeds up the transient time by limiting the inductor current switching in the hysteresis region. The chip size is 1.634 mm2. The input voltage ranges are from 3 V to 3.6 V and the output voltage ranges are from 1 V to 2.5 V. The maximum efficiency is 94.54%.
All of the proposed chips in the thesis are implemented with TSMC 0.35-μm 2P4M CMOS process.

摘要 i
ABSTRACT ii
誌謝 iv
目錄 v
表目錄 ix
圖目錄 x
第一章 緒論 1
1.1相關研究與發展近況 1
1.2研究動機與目的 2
1.3論文架構 3
第二章 切換式直流-直流轉換器之理論分析 4
2.1切換式降壓轉換器穩態分析 4
2.1.1連續時間導通模式(Continuous Conduction Mode，CCM) 6
2.1.2非連續時間導通模式(Discontinuous Conduction Mode，DCM) 9
2.2切換式升壓轉換器穩態分析 11
2.2.1連續時間導通模式(Continuous Conduction Mode，CCM) 13
2.2.2非連續時間導通模式(Discontinuous Conduction Mode，DCM) 15
2.3直流-直流轉換器之定義 16
2.3.1線性調節率(Line Regulation) 16
2.3.2負載調節率(Load Regulation) 17
2.3.3輸出電壓漣波(Output Voltage Ripple) 17
2.3.4效率(Efficiency) 17
2.3.5暫態響應(Transient Response) 18
2.4切換式轉換器之控制技術 19
2.4.1固定導通時間控制 19
2.4.2峰值電流控制 20
2.4.3磁滯電流控制 21
第三章 適應性導通時間控制之定頻降壓轉換器 22
3.1設計目標 22
3.2架構簡介 22
3.2.1運算放大器(Operational Amplifier，OPA) 23
3.2.2適應性導通時間控制器(Adaptive On-Time Controller) 24
3.2.3磁滯比較器(Hysteresis Comparator) 25
3.2.4鎖相鎖頻電路(Phase-Frequency-Locked Loop，PLL) 26
3.2.4.1相位頻率偵測(Phase Frequency Detector) 26
3.2.4.2電荷幫浦(Charge Pump)與二階濾波器(Second Order Filter) 28
3.2.5非重疊電路與驅動電路(Non-overlap and Driver Circuit ) 30
3.3電路模擬 31
3.3.1 Hspice模擬 31
3.4整體電路佈局與量測結果 34
3.4.1 晶片佈局 34
3.4.2 晶片腳位名稱與功能 35
3.4.3 量測環境 37
3.4.4 量測結果 38
3.5 規格表與相關文獻比較 42
第四章 使用連續時間三角積分技術之低雜訊升壓轉換器 44
4.1三角積分調變 44
4.2 三角積分調變器原理 44
4.2.1 奈奎式定理(Nyquist-Rate) 44
4.2.2 超取樣技術(Oversampling) 45
4.2.3 量化誤差(Quantization Error) 45
4.2.4 雜訊移頻技術(Noise Shaping) 47
4.2.5 二階三角積分調變器架構 49
4.2.6 類比數位轉換器效能參數定義 50
4.3架構簡介 51
4.3.1 補償器(Compensator) 52
4.3.2 轉導放大器(Operational Transconductance Amplifier，OTA) 53
4.3.3 二階三角積分電路(2nd-Order Delta-Sigma，Δ-∑) 53
4.3.4 一位元閂鎖比較器(1-Bit Comparator) 55
4.3.5 一位元數位類比轉換器(1-Bit DAC) 55
4.4電路特性模擬 56
4.4.1 Hspice模擬 56
4.5整體電路佈局與量測結果 58
4.5.1 晶片佈局 58
4.5.2 晶片腳位名稱與功能 59
4.5.3 量測環境 61
4.5.4 量測結果 62
4.6 規格表與相關文獻比較 68
第五章 新型主動式電感電流感測技術之磁滯電流控制降壓轉換器 70
5.1架構簡介 70
5.1.1 主動式電感電流感測電路(Active Inductor Current Sensing Circuit) 70
5.1.2 電流產生器(Current Generator) 72
5.1.3 磁滯電流控制(Hysteresis-Current-Controlled，HCC) 72
5.2電路模擬 74
5.2.1 Hspice模擬 74
5.3效率與整體電路佈局 76
5.3.1 效率 76
5.3.2 晶片佈局 76
5.3.3 晶片腳位名稱與功能 77
5.3.4 量測環境 79
5.4 規格表與相關文獻比較 79
第六章 結論與未來展望 81
6.1 結論 81
6.2 未來展望 82
參考文獻 83

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