臺灣博碩士論文加值系統

本論文中，實現一個應用於無線通訊之12位元1GS/s電流導向數位類比轉換器(DAC)，所提出的數位類比轉換器採用分段式電流導向架構，其中最大八個有效位元碼(MSB)轉成溫度計碼，最小四個有效位元(LSB)使用二進位權重碼。此架構中，提出一個行時脈控制器的新技術，用來減少時脈饋入對輸出的失真影響與整體的功率消耗。
所設計的數位類比轉換器採用TSMC 90nm 的製程來實現，在靜態效能上，當有開啟時脈控制器時：差分非線性誤差為0.008LSB，積分非線性誤差為0.019LSB；當關閉時脈控制器時：差分非線性誤差為0.011LSB，積分非線性誤差為0.018LSB。當取樣頻率為1GS/s，輸入訊號為499MHz時，有開啟與關閉時脈控制器的無突波動態範圍(SFDR)分別為85dB與82dB，整個功率消耗為24mW。

In this thesis, A 12-bit 1GS/s DAC for wireless communications is proposed. In order to achieve the high performance requirements, the current-steering architecture is the most suitable and widely used in the present design. The segmented current steering architecture that comprises 8MSB’s thermometer code and 4LSB’s binary-weighted is used. In this design, a new technique of the column clock controller (CCC) is proposed to improve the DAC performance. The Column clock controller (CCC) is able to reduce the clock feed-through effect for DAC and reduce power consumption from switching activity.
The designed DAC implemented in TSMC 90nm CMOS technology. When the CCC is enabled, the simulation results show that INL is 0.019LSB and DNL is 0.008LSB; When the CCC is disabled, the simulation results show that INL is 0.018LSB and DNL is 0.011LSB. When the CCC is enabled and disabled, the SFDR is 85dB and 82dB respectively. The power consumption is 24mW.

摘要 II
ABSTRACT III
LIST OF TABLES VI
LIST OF FIGURES VII
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Organization 4
CHAPTER 2 SURVEY OF CURRENT-STEERING DAC 5
2.1 Introduction 5
2.2 DAC Specification 5
2.2.1 Static Specification 8
2.2.2 Dynamic Specification 11
2.3 Current-steering DAC 13
2.3.1 Binary-Weighted DAC 13
2.3.2 Thermometer-code DAC 14
2.3.3 Segmented DAC 17
2.4 Design Consideration for DACs 21
2.4.1 Cell-Dependent Delay Differences (CDDDs) [29] 22
2.4.2 Output-Dependent Delay Differences (ODDDs) [30] 23
2.4.3 DAC’s Output Impedance and Distortion 25
2.5 Dynamic Element Matching Technique[34] 27
CHAPTER 3 A 12-BIT 1GS/S DAC IN 90NM 30
3.1 Introduction 30
3.2 Proposed Segmentation DAC Architecture 30
3.3 8-bit Thermometer-Coded DAC 32
3.3.1 Unit Current Cells 32
3.3.2 Column Clock Controller (CCC) 35
3.4 4-bit Binary-Weighted DAC 39
3.5 Biasing Circuit 41
CHAPTER 4 SIMULATION AND EXPERIMENTAL RESULTS 42
4.1 Simulation Results 42
CHAPTER 5 CONCLUSIONS AND FUTURE WORKS 49
5.1 Conclusion 49
5.2 Future Works 50
REFERENCES 51

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