|
[1] M. Rostami, F. Koushanfar, and R. Karri, “A primer on hardware security: Models, methods, and metrics,” Proc. IEEE, vol. 102, no. 8, pp. 1283–1295, Aug. 2014. [2] U. Guin, D. DiMase, and M. Tehranipoor, “Counterfeit integrated circuits: Detection, avoidance, and the challenges ahead,” J. Electron. Test., vol. 30, no. 1, pp. 9–23, 2007. [3] R. Torrance and D. James, “The State-of-the-Art in Semiconductor Reverse Engi-neering,” in IEEE/ACM Design Automation Conference, 2011, pp. 333–338. [4] R. Karri, J. Rajendran, K. Rosenfeld, and M. Tehranipoor, “Trustworthy hardware: Identifying and classifying hardware Trojans,” IEEE Comput., vol. 43, no. 10, pp. 39–46, Oct. 2010. [5] SEMI. (2008). Innovation is at Risk: Losses of up to $4 Billion Annually due to IP Infringement. [Online]. Available: http://www.semi.org/ en/Issues/IntellectualProperty/ssLINK/P043785, accessed Jun. 10, 2015. [6] (Jun. 30, 2015). Top 5 Most Counterfeited Parts Represent a $169 Billion Potential Challenge for Global Semiconductor Market. [Online]. Available: http://press.ihs.com/press-release/design-supply-chain/top-5- most-counterfeited-parts-represent-169-billion-potential-cha [7] K. He, X. Huang and S. X. -. Tan, "EM-Based On-Chip Aging Sensor for Detection of Recycled ICs," in IEEE Design & Test, vol. 33, no. 5, pp. 56-64, Oct. 2016. doi: 10.1109/MDAT.2016.2582830 [8] (2005). Defense Science Board (DSB) Study on High Performance Microchip Supply. [Online]. Available: http://www.acq.osd.mil/dsb/ reports/ADA435563.pdf, accessed Mar. 16, 2015. [9] The Copyright Law of the United States and Related Laws Contained in Title 17 of the United States Code, Gov. Printing Office, Washington, DC, USA, 2012. [10] (Jan. 16, 2015). Law on the Circuit Layout of a Semiconductor Integrated Circuits (Act No. 43 of May 31, 1985, as Last Amended by Act No. 50 of June 2, 2006). [Online]. Available: http://www.wipo.int/wipolex/en/details.jsp?id=2626 [11] J. A. Roy, F. Koushanfar, and I. L. Markov, “EPIC: Ending piracy of integrated circuits,” in Proc. Design Autom. Test Europe, Munich, Germany, 2008, pp. 1069–1074. [12] J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, “Security analysis of logic obfus-cation,” in Proceedings of the 49th Annual Design Automa- tion Conference. ACM, 2012, pp. 83–89. [13] J. Rajendran, H. Zhang, C. Zhang, G. S. Rose, Y. Pino, O. Sinanoglu, and R. Karri, “Fault analysis-based logic encryption,” Computers, IEEE Transactions on, vol. 64, no. 2, pp. 410–424, 2015. [14] S. Khaleghi, K. Da Zhao, and W. Rao, “IC piracy prevention via design withholding and entanglement,” in Design Automation Conference (ASP- DAC), 2015 20th Asia and South Pacific. IEEE, 2015, pp. 821–826. [15] B. Liu and B. Wang, “Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks,” in Proceedings of the conference on Design, Automation and Test in Europe. European Design and
Automation Association, 2014, p. 243. [16] S. Dupuis, P.-S. Ba, G. Di Natale, M.-L. Flottes, and B. Rouzeyre, “A novel hard-ware logic encryption technique for thwarting illegal overproduction and hardware trojans,” in On-Line Testing Symposium (IOLTS), 2014 IEEE 20th International. IEEE, 2014, pp. 49–54. [17] R. S. Chakraborty and S. Bhunia, “Harpoon: an obfuscation-based soc design meth-odology for hardware protection,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493–1502, 2009. [18] Y. Lee and N. A. Touba, "Improving logic obfuscation via logic cone analysis," 2015 16th Latin-American Test Symposium (LATS), Puerto Vallarta, 2015, pp. 1-6. [19] N. Zhu, W. L. Goh, W. Zhang, K. S. Yeo and Z. H. Kong, "Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 8, pp. 1225-1229, Aug. 2010. [20] B. Krishnamurthy and I. G. Tollis, "Improved techniques for estimating signal proba-bilities," in IEEE Transactions on Computers, vol. 38, no. 7, pp. 1041-1045, July 1989. [21] V. Camus, J. Schlachter and C. Enz, "A low-power carry cut-back approximate adder with fixed-point implementation and floating-point precision," 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, 2016, pp. 1-6.
|