臺灣博碩士論文加值系統

近幾年由於電腦網路的普及化，資料流量傳輸需求也日漸具增，使得輸入/輸出介面的頻寬變成是眾多系統中的瓶頸。在有線背板通訊系統中，高速資料傳輸會同時遭受到介質損耗和集膚效應，這些現象會使原本傳送的訊號失真，導致嚴重的符際干擾，惡化位元錯誤率。為了減輕符際干擾並改善位元錯誤率，一種解決方式是對傳輸資料做調變，減少系統對通道所需頻寬的要求，來維持訊號完整性。另一種解決方式是利用等化器去補償通道衰減，其中類比等化器、預先強化器和決策回授等化器已經被廣泛應用於通道損耗的補償，然而，一顆等化器可能被應用於不同的長度或板材的通道中，所受到的符際干擾也會不相同，因此可適性等化器也慢慢普及化且實用於背板通訊傳輸。
本論文主要分為兩個部分，在第二章中，利用雙二元調變傳輸來取代傳統二源傳輸，把預先編碼器和雙二源轉換器合併一起，減少硬體的需求，以達到高速低功率的目標，在90奈米CMOS製成下實現一20-Gb/s的收發器，其中我們提中可適性的預先補償器方法，因為發射端沒有眼圖開大小的資訊，所以在預先強化器上做可適性是有點難度，我們在資料傳輸之前，在發射端一端送入一個時脈，經過通道後再接收回發射端，我們可以觀察時脈的振幅大小去決定預先強化器的補償係數。通道越長，衰減也越劇烈，所收到的時脈振幅大小也越小，則補償也要越多。等預先強化器的補償係數決定後，就可以開始進行資料對傳。

在第三章中，我們提出有別於傳統類比方式的高速可適性等化器，我們利用一個非同步時脈且盲目取樣收到的訊號，首先去記綠低頻成分的振幅大小，然後調整高頻成分的振幅大小，目標是讓高頻和低頻成分的振幅大小相同，等效上是完成等化器，在決策回授電路中，比較整流後時脈和資料的大小相同，有衰減的資料，振幅一定比較小，因此可以用來控制決策回授電路的補償係數，此架構在65奈米CMOS製成下實現20-Gb/s數位可適性等化器。

1.Introduction…………………………………………………………1
1.1 WirelineCommunications..............................2
1.2 Overview of thesis..................................5

2.A 20-Gb/s Duobinary Transceiver with an Adaptive Pre-emphasis…………………………………………………………………7
2.1 Motivation..........................................8
2.2 NRZ V.S. Duobinary Modulation......................10
2.2.1 NRZ Signaling................................10
2.2.2 Duobinary Signaling..........................11
2.2.3 NRZ V.S. Duobinary Signaling.................12
2.3 Duobinary Systems and Circuits.....................18
2.3.1 System Architecture..........................18
2.3.2 Transmitter..................................20
2.3.3 Receiver.....................................23
2.4 Adaptive Technique for Pre-emphasis................25
2.5 Experimental Results...............................31
2.6 Conclusion.........................................37

3.A 20-Gb/s Digitally Adaptive Equalizer/DFE with Blind Sampling ………………………………………………………………39
3.1 Motivation.........................................40
3.2 System Architecture................................42
3.3 Adaptive Algorithms and Circuit Design.............43
3.3.1 Adaptive Analog Equalizer Technique..........43
3.3.2 Adaptive DFE Technique.......................49
3.3.3 Detection Circuit and Adaptive Controller....51
3.3.4 Analog Equalizer.............................51
3.3.5 Decision Feedback Equalizer..................56
3.4 Experimental Results...............................59
3.5 Conclusion.........................................64

4.Conclusion and Future Work…………………………………….67
4.1 Conclusion.........................................67
4.2 Future Work........................................68

Bibliography………………………………………………………….69

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