臺灣博碩士論文加值系統

隨著製程技術日趨成熟，輸入電壓也日益降低，諸如28奈米先進製程可以使用低於1伏特之輸入電壓VIN。然而遇到較高的輸入電壓時，耐壓卻成為了ㄧ大難題。因此，疊接架構(如:三級架構)被學者們提出。三級架構不但可以藉由疊接的方式增加電晶體的耐壓，也可同時減少了輸出電壓漣波，藉此達到更穩定的輸出電壓。三級架構可以藉由飛電容將VX節點劃分為三種不同的電壓: VIN, 1/2VIN, and VSS。並且透過電壓轉換比例區分成兩種操作區間。倘若輸出電壓大於50% 輸入電壓，則VX節點電壓將操作於VIN與1/2VIN 之間；反之，若輸出電壓小於50% 輸入電壓，則VX節點電壓將介於1/2VIN與VSS 之間。相較於傳統的二級架構，三級架構將VX節點分劃的方式可以大幅降低電壓漣波。此論文題出了三級單電感三輸出電壓轉換器，並比較了三級架構對於暫態響應之影響。

對於以往的三級架構之論點往往著重於"如何校準飛電容之跨壓於1/2 VIN "以達到最低的輸出電壓漣波與最高的效能。對於穩態而言，此方法將減少了50%電感電流斜率，進而降低輸出電壓漣波。但獲取高效能的同時，卻忽視了暫態響應。當遇到輸出端遭遇抽載電流變化時，將會因為電感電流斜率的抑制，導致反應時間過長、輸出電壓浮動過大。對於多輸出電壓轉換器而言，交叉響應的影響更甚。

此論文對於上述問題提出了"可調式電容技術"。當輸出遭遇抽載變化時，可藉由抽載量改變飛電容的跨壓，進而彌補三級架構暫態響應緩慢的缺點，也同時保有了低電壓輸出漣波與高效能之優勢。

Advanced CMOS devices below 28nm allow supply voltages lower than 1V. For applications with higher input voltage (VIN) in such devices, stacked MOSFET structures with a three-level (3L) technology are commonly employed. The stacked structure can also reduce the output voltage ripple substantially. The three-level topology applies three different voltages, VIN, 1/2VIN, and VSS, to the node VX. The operation mode is determined by the duty cycle (D), i.e., the node VX swings between 1/2VIN and VSS when D < 0.5, and between 1/2VIN and VIN, otherwise (D>0.5). Compare to the conventional two-level converter, the voltage swinging range of node VX is halved, leading to the reduction of the output voltage ripple. The thesis proposed a three-level single-inductor triple-output (SITO) converter and also compares the transient response with the SITO converter without the three-level technique.

In state-of-the-art, the key issue of the three-level topology is how to calibrate the cross voltage of flying capacitor CFLY at the point of 1/2Vin. In general, the restrained output voltage ripple and the flatter inductor current (IL) slope seriously result in worse transient response and severe cross regulation (CR) problems, respectively. The analysis in the thesis shows that the three-level SITO converter achieves a smaller output voltage ripple in steady state, but it causes the problems of slower transient response time, longer recovery time, larger overshoot/undershoot, and severe CR. Thus, it is desired to develop a technique that can adjust the cross voltage of CFLY such that the three-level topology achieves higher efficiency, lower output voltage ripple, and fast transient response simultaneously.

摘 要 i
ABSTRACT ii
誌 謝 iii
Contents iv
Figure Captions vi
Table Captions viii

Chapter 1 Introduction 1
1.1 SIMO converter for wearable devices 1
1.2 Three-level topology 2
1.3 The combination of three-level topology and SIMO converter 5
1.4 Motivation 7
1.5 Thesis organization 7

Chapter 2 Prior Arts for SIMO converter and three-level topology 8
2.1 Prior design for SIMO converter 8
2.1.1 Fixed/Adaptive frequency controller 8
2.1.2 Cross regulation problems 10
2.2 Prior designs for three-level topology 12

Chapter 3 Proposed Three-level SIMO Converter 15
3.1 Architecture of Three-level SITO Converter 15
3.2 Architecture of Superposition ramp control 17
3.3 Architecture of adaptive flying capacitor topology 18

Chapter 4 Circuit Implementations 20
4.1 Superposition ramp control 20
4.1.1 Twelve operation modes 23
4.1.2 Voltage summation circuit 25
4.2 Driver with Level shift & deadtime control 26
4.3 Adaptive Flying capacitor topology 27
4.3.1 Error amplifier with the embedded comparator 30
4.3.2 CFLY controller 31

Chapter 5 Experimental Results 33
5.1 Chip Micrograph 33
5.2 Comparison of the SIMO converter within and without the AFC
topology 34
5.3 Steady state performance 37
5.4 Statistic Results and Comparison Table 38

Chapter 6 Conclusion and Future Work 39

Reference 40

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