臺灣博碩士論文加值系統

中文摘要
對於極複雜的系統單晶片測試技術來說， 使用增加硬體電路測試(Built-In Self-Test, BIST or scan chain insertion)，雖然可以得到較高的故障涵蓋( fault coverage)，但同時會產生高功率消耗以及電路面積增加的問題。為了解決上述兩項缺點，以微處理器核心指令集為基礎，針對嵌入式處理器的軟體自我測試方式近年來已經成為另外一種測試的主流方式。軟體自我測試方式是利用微處理器本身提供的指令集，以及自行撰寫的組合語言(assembly codes)，建立成一組一組的測試程式(test program candidates)。使用者可使用這些測試程式針對電路做偵錯的動作，同時記錄每一個時序週期(clock cycle)產生的信號，這些信號可稱之為測試信號(test vectors)。將得到的測試信號轉成標準的測試語言程式(Standard Test Interface Language, STIL)，測試語言程式經由故障模擬器（fault simulator）與電路檔案一起做模擬，可得到故障涵蓋、故障辭典(fault dictionary)。
本研究提出一個高準確性的自動化故障模擬器(Automatic Fault Simulator)用以計算使用者所提供的測試程式。使用者可根據故障涵蓋以及故障辭典的結果，修改或是組合出更好的測試程式以提高測試程式的故障涵蓋，進而媲美使用增加硬體電路的方式；同時我們發展出一套流程去確認故障模擬技術是否符合原來所給予的測試程式而沒有更動原來的功能。
最後利用Parwan微處理器和8051微控制器作為測試範例、驗證我們所提出的方法，並且比較其結果。

Abstract
Software self-testing for embedded processor cores based on their instruction sets is a topic of increasing interest. Since it provides an excellent test resource partitioning technique for sharing the testing task of complex System-on-Chip (SoC) between slow, inexpensive testers and embedded code stored in memory cores of the SoC. Although BIST or scan chain can provide higher fault coverage for complex SoC, higher power consumption and area overhead are two issues that should be solved. Software self-testing concept is to utilize the instruction sets provided by microprocessors or microcontrollers. The users can establish test program candidates by combining the instructions. Users can perform logic simulation and detect structural faults with test program candidates, record the signals in every clock cycle at the same time. The signals which were recorded in every clock cycle are called test vectors.
The purpose of proposed fault simulator is to transfer test vectors into test file like STIL (standard test interface language) which can be accepted by fault simulator, and evaluate fault coverage, fault dictionary with circuit files.
In the thesis, we present a high accuracy fault simulator for user defined test program candidates to evaluate fault coverage by performing fault simulation without modifying the original design. We acquire some useful information like fault coverage, fault dictionary through fault simulation. Users can compare the quality of these test program candidates and find out which candidate can detect the most faults. In addition, higher fault coverage could be achieved by combining test program candidates or finding some specific ordering. Some experiments are established to validate the proposed fault simulator.
The Parwan and 8051 IP cores are taken for experiments. Some test programs come from public literature and others are from public websites. Before performing fault simulation, the correctness of function was validated in the beginning. Simulation results are shown to validate the proposed technique.

中文摘要
Chapter 1. Introduction 01
Chapter 2. Self-Test Methodology 05
2.1 Overview 05
2.2 Test Evaluation framework 06
2.3 Contribution 08
Chapter 3. Proposed Translation Method and Validation Flow 09
3.1 Proposed Translation Method 09
3.1.1 Rule 1: Input and Output Vectors Timing Selection 09
3.1.2 Rule 2: Effect of Bi-directional Bus Control Signals 10
3.2 Function Validation Flow for Proposed Method 12
3.3 A Design for Modeling Bi-directional Bus 14
3.3.1 Fault Simulation with Simplified Design 17
3.3.2 Methods for Validating the Proposed Translation 21
3.3.3 Logic Contention and Bus Contention Analysis 22
Chapter 4. STIL Format Conversion 24
4.1 Introduction about STIL 24
4.2 Automatic STIL Conversion with Dumped Vectors 26
Chapter 5. Simulation Result 28
5.1 Case Study: Parwan 28
5.1.1 Fault Simulation Flow 30
5.1.2 Test Pattern Extraction with the Proposed Method 31
5.1.3 Comparison between Public Literature 33
5.1.4 Bus Contention Analysis and Validation for Proposed Method 34
5.2 Case Study: 8051 36
5.2.1 8051 Fault Simulation Flow 38
5.2.2 Test Pattern Extraction and Fault Simulation for 8051 40
5.2.3 Experimental Results and Validation 41
Chapter 6. Conclusion and Future Work 42
Bibliography 43
List of Figures
List of Tables

Bibliography

[1] V.D.Agrawal et al., “BIST for digital Integrated Circuits”, AT&T Tech. Journal, March 1994, pp30.
[2] J.Shen, J.Abraham, “Native mode functional test generation for processors with applications to self-test and design validation”, ITC 1998, pp. 990-999.
[3] K.Batcher, C.Papachristou, “Instruction randomization self test for processor cores”, VTS 1999, pp. 34 – 40.
[4] K.Radecka, J.Rajski, J. Tyszer, “Arithmetic built-in selftest for DSP cores,” IEEE Trans. on CAD, vol.16, no.11, Nov. 1997, pp. 1358–1369.
[5] J.Rajski, J.Tyszer, “Arithmetic Built-In Self-Test for Embedded Systems”, Prentice Hall, 1997.
[6] S.Hellebrand, H.-J.Wunderlich, “Mixed-mode BIST using embedded processors”, ITC 1996, pp. 195 – 204.
[7] R. Dorsch and H.-J. Wunderlich, “Accumulator based deterministic BIST”, ITC 1998, pp. 412 – 421.
[8] L.Chen, S.Dey, “Software-Based Self-Testing Methodology for Processor Cores”, IEEE transactions on computer-aided design of integrated circuits and systems, Vol. 20, No. 3, Mar 2001
[9] L.Chen, S.Dey, “A scalable Software-based Self-Test Methodology for Programmable Processor”, DAC 2003, June 2-6.
[10] W.-C. Lai, A. Krstic, and K.-T. Cheng, “On testing the path delay faults of a microprocessor using its instruction set,” Proc. 18th VLSI Test Symp., Montreal, Canada, May 2000, pp. 15-20.
[11] L. Chen, X. Bai, and S. Dey, "Testing for interconnect crosstalk defects using on-chip embedded processor cores," J. Electronic Testing: Theory and Applications, vol.18, (no.4), August 2002, pp. 529-538.
[12] A.Passhalis, D.Gizopoulos, N.Kranitis, M.Psarakis, Y.Zorian, “Deterministic Software-based Self-Testing of Embedded Processor Cores”, Design Automation and Test in Europe 2001, Munich, Germany, March 2001.
[13] “A.Passhalis, D.Gizopoulos, N.Kranitis, M.Psarakis, Y.Zorian, “Effective Softare-Based Self-Testing of Embedded Processor Cores”, Proceeding of the 2002 design, Automation and Test in Europe Conference and Exhibition (DATE2002).
[14] http://grouper.ieee.org/groups/1450/index.html.
[15] http://cadlab.ece.ucsb.edu/~wlai/Parwan/.
[16] http://aspire.ucsd.edu/~lichen/260c/parwan/.
[17] “Platform-based Testbench Generation,” R. Henftling, A. Zinn, M. Bauer, W. Ecker, M. Zambaldi, Proceedings of the Design,Automation and Test in Europe Conference and Exhibition (DATE’03).
[18] “ST: PERL package for simulation and test environment,” Kobayashi, K.; Onodera, H.; Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, Volume: 5, 6-9 May 2001.
[19] Marcio T. Oliveira, Alan J. Hu, “High-level Specification and automatic generation for IP-interface monitors,” DAC 2002, June 10-14.
[20] Z.Navabi, “Verilog Computer-Based Training Course”, McGraw-Hill, 2002.
[21] Z.Navabi, “VHDL: Analysis and Modeling of Digital Systems”, McGraw-Hill, 1993.
[22] F. Corno, M. Sonza Reorda, G. Squillero, M. Violante, "On the Test of Microprocessor IP Cores," DATE2001: IEEE Design, Automation & Test in Europe Conference, Munich (Germany), 13-16 March 2001, pp. 209-213.
[23] F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero, "Automatic Test Program Generation from RT-level Microprocessor Descriptions," ISQED2002: 3rd International Symposium on Quality Electronic Design, March 18-21, 2002, San Jose, California (USA), pp. 120-125.
[24] VerilogHDL “A Guide to Digital Design and Synthesis” Samir Palnitkar.
[25] N. Kranitis, G. Xenoulis, A. Paschalis, D. Gizopoulos, Y. Zorian, “Application and Analysis of RT-level Software-Based Self-Testing for Embedded Processor Cores,” International Test Conference: ITC 2003.
[26] 8051 slides: http://www.utdallas.edu/%7Eparik/ee4380_fall01/.
[27] http://www.opencores.org.