臺灣博碩士論文加值系統

本論文研製之應用於DVD-ROM 之類比前端電路以台灣積體電路公
司之0.35 微米金氧半場效電晶體之製程技術完成晶片製作。近年來
隨著電腦多媒體之盛，快速、高容量儲存媒介需的求也隨之增加。而
DVD 因為此一優點，成為目前非當耀眼的一個新科技產物。然而目前
在DVD-ROM 的前級線路上，大多是採用雙載子金氧半場效電晶體製程
來製造，因此價格也就相對的較高。在此論文中採用CMOS 的製程來
設計DVD-ROM 的前級線路並且能應用在十六倍速以上。在自動增益控
制迴路的捕捉時間上，可以調整迴路濾波器及積分器外部的電阻及電
容值來改變，以滿足不同速度的DVD，並加入飄移電壓補償電路以及
在最後設計一高速ADC(450MBs/s)來滿足十六倍速的DVD 規格。

In the thesis, analog front end circuits for high speed DVD-ROM application are proposed. It can be utilized in sixteen-folds or high speed DVD-ROM. The performance of the circuit can meet the rapid demand in the future (more than 16X). In the past years, the DVD system is almost realized by BiCMOS technology. In order to reduce its cost and increase density of transistors on the same chip, CMOS technology is chosen.
The compensation technology proposed in transimpedance amplifier can broaden its bandwidth without degrading its gain. And this method can be realized by digital CMOS process without reducing its influence. An offset-free, infinite DC gain integrator is established in a feedback loop about the uncompensated circuit, resulting in a high pass system output response. The “ideal” integrator is realized via the use of a counter resulting in the cancellation of the signal’s DC offset. In order to realize this integrator in the analog domain, binary counter together with a digital-to-analog converter as an “ideal” integrator is included. It is the simplest circuit to cancel the DC offset. The speed limitation of the AGC is dominated by the gain and buffer stage. This is because of the output pad capacitance loading (~25pF). If AGC does not have to drive the large capacitor pad loading, the bandwidth will become wider. The acquisition time of AGC can be adjusted by varying the dc bias point in loop filter and integrator to satisfy the requirement of different speed DVD-ROM.
Following the AGC, the type of ADC adopted is flash ADC. In order to compensate the performance of INL and DNL, averaging network method is included. Thanks this technology it also can reduce the influence of random offset caused by process.

Chapter 1 Introduction .................................................................................................. 1
1.1 MOTIVATIONS.............................................................................................. 1
1. 2 PRML READ CHANNEL FOR DVD APPLICATION ................................ 1
1. 3 THESIS ORGANIZATION ........................................................................... 2
Chapter 2 Transimpedance Amplifier ........................................................................... 4
2.1 INTRODUCTION........................................................................................... 4
2. 2 TRANSIMPEDANCE AMPLIFIERS ........................................................... 4
2. 3 THE NOVEL CMOS TRANSIMPEDANCE AMPLIFIER .......................... 7
Chapter 3 Offset Cancellation Circuit......................................................................... 20
3.1 INTRODUCTION......................................................................................... 20
3. 2 CIRCUIT PRINCIPLE................................................................................. 20
3. 3 CIRCUITS AND SIMULATIONS............................................................... 23
3. 4 OFFSET CANCELLATION SIMULATION............................................... 28
Chapter 4 Automatic Gain Control Circuit ................................................................. 33
4.1 INTRODUCTION......................................................................................... 33
4.2 AGC ARCHITECTURE ............................................................................... 33
4.3 CIRCUITS AND SIMULATIONS................................................................ 37
4.4 AGC LOOP SIMULATION.......................................................................... 45
Chapter 5 Analog-to-Digital Converter with Offset Averaging Technology............... 50
5.1 INTRODUCTION......................................................................................... 50
5.2 ADC ARCHITECTURE............................................................................... 50
5.3 OFFSET AVERAGING................................................................................ 52
5.4 CIRCUITS AND SIMULATIONS............................................................... 53
Chapter 6 Conclusions ................................................................................................ 66

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