臺灣博碩士論文加值系統

隨著行動化個人多媒體時代的來臨, 具有較高功率轉換效率之D類音頻放大器逐漸的備受重視。但是其線性度較差的缺點往往需要透過較複雜的時脈調變機制或是補償控制來彌補。這對於某些需求僅僅著重在高輸出功率，高線性度，低失真的傳統應用來說，並不一定是最適合架構。
此篇論文將以業界的商用規格為目標，設計具有高輸出功率, 低失真之AB類線性音頻放大器。並包含音量控制，耳機輸出，短路保護等功能。
一般而言，線性音頻放大器之負載阻抗約為8歐姆，輸出級必須具備極大的電流驅動能力。輸出級的設計對放大器的靜態耗電流、功率轉換效率與線性度有決定性的影響。本論文創新之處在於利用精簡的架構控制輸出級之靜態耗電流，避免靜態耗電流與線性度受到製程漂移之影響，造成不穩定的現象。此AB類輸出級的架構採用共源極組態之功率電晶體並搭配誤差放大器，藉由降低誤差放大器之增益達到控制靜態耗電流的目標。此誤差放大器之增益將隨著輸出功率增加而提高，當增益提高時，線性度也隨之上升。另外，誤差放大器寬廣的輸出共模範圍，使受其控制的功率電晶體可以用較小的面積達到所需的輸出功率。
晶片製作是採用聯華電子0.5um +/-20V2P2M製程。並且可在寬廣供應電壓範圍10~18V之間使用。當供應電壓為18V，負載為8歐姆，輸出功率為2W時，總諧波失真大約為0.060 %

With the advent of a highly-mobilized and individualized multimedia age, Class-D audio amplifiers with better power efficiency, among the applications of its kind, have gained a lot of attentions. However, in view of the fact that traditionally high output power, good linearity, and low distortion are expected in amplifiers alike, Class-D audio amplifiers may not be an ideal choice since it requires a complicated clock modulation or a compensatory control mechanism to make up to its poor output linearity. To look for an applicable alternative, therefore, this thesis puts forth a Class-AB linear audio amplifier that not only meets the design specification of business application, but also equips with features such as volume control, earphone output ports, short-circuit protection, and other functions desired in a multimedia product.
In general, a linear audio amplifier has a load impedance of approximately 8 ohm, so its output stage must have a compatibly large current drive, whose design has a significant influence on the quiescent current, power efficiency, and linearity. These deciding factors in designing a linear audio amplifier thus reveal the originality of this thesis: to rid the unwanted quiescent current of the output stage and unstable linearity resulted from process variation with a succinct structure. The Class-AB output stage adopts common-source power transistors with error amplifiers. By decreasing the gain of the error amplifier, the quiescent current is successfully controlled. Since the gain of the error amplifier will increase as the output power rises, it will therefore enhance the linearity. Besides, its output common mode range is the same as the supply voltage, which is sufficient enough to drive a smaller-sized power transistor to achieve the desired output power.
The chip is fabricated by the UMC 0.5um +/-20V2P2M high voltage process. It could undertake a high supply voltage ranging from 10V to 18V. The total harmonic distortion is approximately 0.060 % provided that the load impedance is 8 ohm and the output power is 2 watt under an 18V supply voltage.

ABSTRACT (CHINESE) i
ABSTRACT (ENGLISH) ii
ACKNOWLEDGEMENTS iv
CONTENTS v
TABLE CAPTIONS vii
FIGURE CAPTIONS viii

CHAPTER 1 Introduction 1
1.1 Background 1
1.1.1 Review of the class-AB output stage architecture 2
1.2 Motivations 20
1.3 Main result 21
1.4 Thesis organization 21
CHAPTER 2 Architecture and circuit design 22
2.1 Design specification and consideration 22
2.2 Full circuit architecture 23
2.3 Buffered amplifier 24
2.3.1 Architecture of buffered amplifier 25
2.3.2 Error amplifier for output buffer 25
2.3.3 Short circuit protection 31
2.3.4 Frequency compensation 35
2.4 Volume control circuit 37
2.5 DC control 10 level volume 38
2.6 Reference voltage generator 41
CHAPTER 3 Simulation result and discussion 42
3.1 Chip layout 42
3.2 Pre-simulation result and Monte Carlo analysis 44
3.2 Post-Simulation result 47
3.3 Discussion 52
CHAPTER 4 Conclusions and future works 53
4.1 Conclusions 53
4.2 Future work 53
REFERENCES 55

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