臺灣博碩士論文加值系統

　　在本論文中，提出以0.8um互補式金氧半製程設計和製造出八位元每
秒62.5百萬次取樣速率的高速類比至數位轉換器。在時脈為125百萬赫茲
下，這個類比至數位轉換器設計成只有八奈秒的取樣時間（其中包含二奈
秒的非重疊時間）。八位元每秒12.5百萬次取樣速率的類比至數位轉換器
小單元是以四級的架構來實現的，此架構不需要用到高增益或大擺幅的運
算放大器來設計。為了改善取樣速率提昇五倍的速度，平行處理應用在五
個並聯連接的類比至數位轉換器上。此線性誤差在二分之一的最小有效位
元之內，佈局後的模擬結果顯示類比至數位轉換器小單元在每秒12.5百萬
次取樣速率下有八位元的解析度。每秒62.5百萬次取樣速率的並聯類比至
數位轉換器的核心面積為3.2毫米×4.6毫米，而功率大約消耗150毫瓦。

In this thesis, an 8-bit 62.5MS/sec A/D converter designed and
fabricated in a 0.8um CMOS process, is presented. The A/D
converter was designed to have a sampling time of 8ns(including
the nonoverlapping time with 2ns) at clock rate of 125MHz. The
8-bit 12.5MS/sec A/D converter cell is implemented by a four-
stage architecture. This structure can be designed without the
operational amplifiers with either high gain or a large output
swing. The parallel processing is applied to the five A/D
converters connected in parallel to improve the conversion rate
up to five times speed. The linearity error is within 1/2 LSB.
The post-simulation result shows the throughout rate can be
12.5MS/sec with 8-bit resolution for the A/D converter cell.
The core of the 62.5MS/sec parallel A/D converter array
occupies an area of 3.2mm×4.6mm, and the power consumption is
about 150mW.