臺灣博碩士論文加值系統

由於現今無線通訊系統對於高傳輸速率之需求，促使IEEE 802.11a協定成為近年發展之主流，其傳輸速率可高達54 Mbps。為了使得射頻接收機在接收天線端之強訊號仍操作於線性區，低雜訊放大器必須具有可變增益之功能，以避免影響下一級電路之正常運作。傳統的可變增益低雜訊放大器主要採用串接架構，由於串接架構中包含放大器、衰減器與緩衝器等三個組態，而組態之間必須做耦合與匹配，且使用的元件數量較多，造成整體電路之複雜性與功耗提升。

本論文主要利用雙組態架構簡化電路複雜性，並運用TSMC 0.18 μm CMOS製程開發可應用於IEEE 802.11a協定之可變增益低雜訊放大器設計；在不犧牲增益之下，降低該電路之功耗，達到可變增益之效果且具有良好的輸入輸出匹配，整體電路包含一個電流再生架構之放大級電路、可變阻抗架構之負載級電路、源極隨耦器架構之緩衝級電路以及N型半導體負載與源極退化架構之輸入級電路。

本論文所開發之可變增益低雜訊放大器其操作頻率為5.2 GHz，符合IEEE 802.11a應用之頻率範圍(5-6 GHz)，晶片尺寸為1.1 mm × 1.1 mm。經由量測結果顯示，其最高增益可達15.29 dB且其最低增益約為與8.19 dB，顯見其可變增益範圍將近7.1 dB。另一方面，該放大器電路之輸入反射損耗相當低，僅僅只有-16.17 dB(最高增益模式)/-15.2 dB(最低增益模式)以及輸出反射損耗非常低，僅僅只有-17.22 dB(最高增益模式)/-19.1 dB(最低增益模式)；同時，具有高隔離度之表現，僅僅只有-39.42 dB(最高增益模式)/-38.72 dB(最低增益模式)。最後，本論文所開發之晶片在1.6 V之偏壓下，其DC消耗功率相當低，僅僅只有16.05 mW(最高增益模式)/15.3 mW(最低增益模式)。

The IEEE 802.11a has become the mainstream protocol used in modern wireless communication system due to its high propagation rate of data (54 Mb/s). In order to keep RF receiver to operate at linear region under receiving strong signal, the gain of low noise amplifier must be tunable to avoid influencing the subsequent block. Traditional variable gain low noise amplifier is mainly adopted in cascade. Owing to the cascade includes amplifier, attenuator and buffer stages, the more complexity and power consumption increased.

This thesis utilizes dual stage to simplify complexity of the circuit and variable gain low noise amplifier fabricated in TSMC 0.18 µm CMOS technology for IEEE 802.11a application. Without sacrificing gain, the variable gain low noise amplifier employ current-reuse structure to amplifier stage to reduce power consumption, variable-impedence structure to load stage to achieve variable gain, source follower structure to buffer to improve output matching, N-type diode load and source-degeneration structure to input stage to improve input matching.

The proposed variable gain low noise amplifier with 1.1 mm × 1.1 mm chip size and its 5.2 GHz operating frequency is well suited for IEEE 802.11a (5~6 GHz) application. Measurement resutls demonstrate the highest and lowest gain of 15.29 and 8.19 dB respectivly, the gain tuning range is approximated as 7.1 dB. Moreover, the amplifier shows input return loss of -16.17 dB (highest gain mode)/-15.2 dB (lowest gain mode) and very good output return loss of -17.22 dB (highest gain mode)/-19.1 dB (lowest gain mode). Simultaneously, the amplifier shows isolation of -39.42 dB (highest gain mode)/-38.72 dB (lowest gain mode). Finally, a moderate consuming power are 16.05 mW (highest gain mode)/15.3 mW (lowest gain mode) of such varible gain low noise amplifier can be achieved from 1.6 V supply voltage.

摘要................................................................................................i
Abstract..........................................................................................ii
誌謝................................................................................................iv
目錄................................................................................................v
圖目錄.............................................................................................vii
表目錄.............................................................................................ix
第一章 緒論.....................................................................................1
1-1 研究背景..............................................................................1
1-1-1 應用於IEEE 802.11a 通訊協定.....................................1
1-1-2 射頻接收機架構之概述.................................................3
1-1-3 傳統低雜訊放大器之簡介.............................................4
1-1-4 傳統可變增益低雜訊放大器之簡介...............................5
1-2 研究動機..............................................................................7
1-3 論文架構..............................................................................8
第二章 低雜訊放大器之原理概述....................................................9
2-1 低雜訊放大器之重要性能參數.............................................9
2-1-1 散射參數......................................................................9
2-1-2 功率增益......................................................................12
2-1-3 穩定度..........................................................................14
2-1-4 雜訊指數......................................................................15
2-1-5 線性度..........................................................................17
2-2 典型低雜訊放大器之電路架構.............................................20
第三章 可變增益低雜訊放大器之設計.............................................22
3-1 應用於IEEE 802.11a之可變增益低雜訊放大器設計............22
3-2 預計規格表..........................................................................35
3-3 設計流程..............................................................................35
第四章 結果與討論..........................................................................37
4-1 實際電路之佈局與考量........................................................37
4-2 量測考量..............................................................................39
4-3 模擬與量測結果...................................................................41
4-3-1 最高/最低增益模式之模擬與量測結果...........................41
4-3-2 可變增益低雜訊放大器之性能比較...............................49
第五章 結論與未來展望...................................................................51
5-1 結論.....................................................................................51
5-2 未來展望..............................................................................53
參考文獻.........................................................................................54

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