臺灣博碩士論文加值系統

本篇論文提出一個低耗能12位元連續漸近式類比數位轉換器的設計（SAR ADC）。此類比數位轉換器組成元件有取樣保持電路（S/H）、比較器、數位類比轉換器（DAC）以及連續漸近式訊號產生器（SAR）。針對生醫訊號DC訊號會飄動的現象，在此提出一個新的軌對軌比較器，把SAR ADC系統設計成可軌對軌的輸入範圍。此外在DAC部分移除了參考電壓的使用，克服因參考電壓的不匹配所帶來性能上誤差。在耗能方面，整個系統上沒有使用放大器，且針對比較器在時間上做開關控制能有效的降低功率的損耗。使用台積電0.18微米1P6M的製程。供應電壓為1.8V，在取樣頻率200 kHz有效訊號頻寬10 kHz下實際量測後，平均消耗功率76.32-μW，SNDR達到49.7dB。整個晶片的核心面積為0.082毫米平方。

Generally, the signal bandwidth of biomedical signals ( EEG, ECG, Oxygen Saturation, Heart Rate, Temperature ) is under 10 kHz [29]. For portable biomedical acquisition system, lower power A/D converter is an important component that can determine the performance of whole system.
In this paper, a 1.8V 12-bit 200-kS/s successive approximation analog-to-digital converter (SAR ADC) is presented in this work. In order to overcome the biomedical signal’s dc shift and acquire accurately, the proposed ADC receives rail-to-rail input and performs 12-bit resolution (10-bit is the basic requirement for normal biomedical signal). Moreover, the digital-to-analog converter without reference voltage (WRV) and binary capacitor array is also adopted to reduce the total chip area. With these properties, the proposed ADC can be easily integrated with other components in biomedical acquisition system at low cost. The proposed converter is designed in a 0.18-μm CMOS process for biomedical application. Simulation results show that both INL and DNL errors are well controlled in 0.34LSB. The measurement results show SNDR is 49.7 dB and the total power consumption is 76.32-μW at 1.8V supply voltage. The core area of the test chip is 0.082 mm2.

TABLE OF CONTENTS III
LIST OF TABLES V
LIST OF FIGURES VI
Symbols and Abbreviations IX
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization 3
Chapter 2 Proposed ADC for Biomedical Application 4
2.1 The architectures of A/D converters 4
2.2 The principle of Successive approximation ADC 6
Chapter 3 Building Block Design 10
3.1 S/H Circuit 10
3.2 Digital to Analog Converter 15
3.2.1 Traditional DAC Structure 15
3.2.2 Proposed DAC Structure 18
3.2.3 Realize scale capacitor Cs 23
3.2.4 Nonlinearity of DAC 24
Effect of Nonlinearities on Code Performance 24
3.2.5 Arrangement of Capacitor Array 26
The geography of capacitor array 26
Metal-insulator-metal ( MIM ) capacitor model 29
3.3 Latch comparator 30
3.3.1 Adapted Comparator 32
3.4 Successive Approximation Register 39
3.5 Operation waveforms of signals 42
Chapter 4 Experiment Result 44
4.1 Quantization Noise 44
4.2 Performance Metrics 45
4.3 FFT Test 49
4.4 Code-Density Testing 51
4.5 Power and Performance Simulation 53
4.6 Layout Arrangement 55
4.7 Test Board and Measurement Environment 58
4.8 Measurement Results 60
Chapter 5 Conclusions and Future Work 68
5.1 Conclusions 68
5.2 Future Work 69
Appendix 70
Reference 76

[1]David A. Johns and Ken Martin,”Analog Integrated Circuit Design”
[2]Allen/Holberg,”Cmos Analog Circuit Design 2th”
[3]Razavi,”Design of Analog CMOS Intrgrated Circuits”
[4]Rudy van de Plassche, “CMOS INTEGRATED ANALOG-TO-DIGITAL AND DIGITAL–TO-ANALOG CONVERTERS”
[5]Gilbert Promitzer, “12-bit Low-Power Fully Differential Switched Capacitor Noncalibrating Successive Approximation ADC with 1 MS/s”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 7, JULY 2001
[6]Jens Sauerbrey, Doris Schmitt-Landsiedel, and Roland Thewes,” A 0.5-V 1-μW Successive Approximation ADC”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 7, Brief Papers, JULY 2003
[7]Christian C. enz, and Gabor C. temes, “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization”, PKOCbtDlNGS OF THE IEEE, VOL 84, NO 11, NOVEMBER I996
[8]Kul B. Ohri and Michael J. Callahan JR. , ”Integrated PCM Codec”, IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. COM-27, NO. 2, FEBRUARY 1979
[9]Siamak Mortezapour and Edward K. F. Lee,“A 1-V, 8-Bit Successive Approximation ADC in Standard CMOS Process”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 4, APRIL 2000
[10]JAMES L. McCREARY, AND PAUL R. GRAY, “AII-MOS Charge Redistribution Analog-to-Digital Conversion Techniques—Part I”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, DECEMBER 1975
[11]RICARDO E. SUAREZ, PAUL R. GRAY, AND DAJ’ID A. HODGES, “AII-MOS Charge Redistribution Analog-to-Digita Conversion Techniques–-Part II”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, DECEMBER 1975
[12]Chi-Sheng Lin and Bin-Da Liu, “A New Successive Approximation Architecture for Low-Power Low-Cost CMOS A/D Converter ”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003
[13]Kul B. Ohri and Michael J. Callahan JR. ,” Integrated PCM Codec”, IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. COM-27, NO. 2, FEBRUARY 1979
[14]李國銘, “應用於無線感測網路之超低號能連續近似式類比數位轉換器之設計”, 交通大學 95年7月
[15]A. Rossi and 6.Fu cili, ‘Nonredundant successive approximation register for AD converters’, ELECTRONICS LETTERS 6th June 1996 Vol. 32 No. 12
[16]Kihyuk Sung and Lee-Sup Kim, “A High-Resolution Synchronous Mirror Delay Using Successive Approximation Register”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004
[17]唐佩忠, “VHDL 與數位邏輯設計”, 高立出版
[18]王進賢, “VLSI 電路設計”, 高立出版
[19]Takeshi Yoshida, Miho Akagi, Mamoru Sasaki and Atsushi Iwata, “A 1V supply successive approximation ADC with rail-to-rail input voltage range”, ISCAS, 2005
[20]Jiren Yuan and Christer Svensson, “A 10-bit 5-MS/s Successive Approximation ADC Cell Used in a 70-MS/s ADC Array in 1.2-pm CMOS”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, NO. 8, AUGUST 1994
[21]K. Kiyoyama, M. Onoda, and Y. Tanaka, “A Low Current Consumption CMOS Latched Comparator for Body-implanted Chip”, ISCAS, 2005
[22]許哲豪, “使用單一參考電壓的12位元全差動切換電容逐漸趨近式類比數位轉換器” , 成功大學 92年7月
[23]Hwang-Cherng Chow, Bo-Wei Chen, Hsiao-Chen Chen and Wu-Shiung Feng, “A 1.8V, 0.3mW, 10-Bit SA-ADC with New Self-Timed Timing Control for Biomedical Applications, ISCAS, 2005
[24]E. A. Vittoz, “Low-Power Design: Ways to Approach the Limits,” in Dig. Tech.Papers International Solid-State Circuits Conference, pp. 14–18, Feb. 1994.
[25]Brian P. Ginsburg and Anantha P. Chandrakasan, “Dual Scalable 500MS/s, 5b Time-Interleaved SAR ADCs for UWB Applications”, IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2005
[26]Michael D. Scott, Bernhard E. Boser, and Kristofer S. J. Pister, “An Ultralow-Energy ADC for Smart Dust”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 7, JULY 2003
[27]Ayaskant Shrivastava, “12-bit non-calibrating noise-immune redundant SAR ADC for System-on-a-chip “, ISCAS 2006
[28]Kyriacou E, Pavlopoulos S, Berler A, Neophytou M, Bourka A, Georgoulas A, Anagnostaki A, Karayiannis D, Schizas C, Pattichis C, Andreou A, Koutsouris D,: ‘Multi-purpose HealthCare Telemedicine Systems with mobile communication link support’ BioMedical Engineering OnLine 2003, 2:7.
[29]J. Goes, , N. Paulino, H. Pinto, R. Monteiro, Bruno Vaz, and A. S. Garção , “Low-Power Low-Voltage CMOS A/D Sigma-Delta Modulator for Bio-Potential Signals Driven by a Single-Phase Scheme” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 52, NO. 12, DECEMBER 2005
[30]Taiwan Semiconductor Manufacturing Co. (TSMC)
[31]Mikko Waltari “CIRCUIT TECHNIQUES FOR LOW-VOLTAGE AND HIGH-SPEED A/D CONVERTERS”, Helsinki University of Technology, Electronic Circuit Design Laboratory Report 33, Espoo 2002
[32]LM1086 datasheet, National Semiconductor, June 2005