[1] R. Pyndiah, A. Glavieux, A. Picart, and S. Jacq, “Near optimum decoding
of product codes,” in Proc. IEEE GLOBECOM’94 Conf., vol. 1/3, San
Francisco, pp. 339-343, Nov.-Dec. 1994.
[2] O.Aitsab and R. Pyndiah, “Performance of Reed-Solomon block turbo code,”
in Proc. IEEE Global Telecommun. Conf., vol. 1-3, London, U.K., pp. 121-
125, Nov. 1996.
[3] E. Piriou, C. Jego, P. Adde, R. Le Bidan, and M. Jezequel, “Efficient
architecture for Reed Solomon block turbo code,” ISCAS 2006 :
International Symposium on Circuits and Systems, Kos, Greece, pp. 3682-
3685, May 21-24, 2006.
[4] D. Chase, “A class of algorithms for decoding block codes with channel
measurement information,” IEEE Trans. Inform. Theory, vol IT-18, no. 1,
pp.170–182, Jan. 1972.
[5] P. Elias, “Error-free coding,” IRE Trans. Inform. Theory, vol. IT-4, pp.
29-37, Sept. 1954.
[6] C. Berrou, A. Glavieux, and P. Thitimajshima, “Near Shannon limit error-
correcting coding and decoding: Turbo-codes (1),” IEEE Int. Conf. on
Communications ICC’ 93, vol. 2/3, pp. 1064–1071, May 1993.
[7] R. Pyndiah, “Near-optimum decoding of product codes: Block turbo codes,”
IEEE Trans. Commun., vol. 46, no. 8, pp. 1003–1010, Aug.1998.
[8] J. Hagenauer, E. Offer, and L. Papke, “Iterative decoding of binary block
and convolutional codes,” IEEE Trans. Inform. Theory, vol. 42, pp. 429-
445, Mar. 1996.
[9] R. Zhou, R. Le Bidan, R. Pyndiah, and A. Goalic, “Low-complexity high-
rate Reed-Solomon block turbo codes,” IEEE Trans. on Communications, vol.
55, no. 9, pp. 1656–1660, 2007.
[10] S. W. Wei and C. H. Wei, “High-speed decoder of Reed-Solomon codes,”
IEEE trans. Comm., Vol. 41, No. 11, pp. 1588-1593, November 1993.
[11] 蔡明希, “快速步階式里德-所羅門解碼器之硬體實現,” 中華大學碩士論文, 2006.[12] 陳棟洲, “Step-by-Step Reed-Solomon Decoding Algorithm for Error/Erasure
Correcting, 錯誤及擦失更正之步階式里德-所羅門解碼演算法,” 國立交通大學博士論文,
2003.
[13] J. L. Massey, “Step-by-step decoding of the Bose-Chaudhuri-Hocquenghem
codes,” IEEE Trans. Inform. Theory, vol. IT-11, pp. 580-585, Oct. 1965.
[14] T. C. Chen, C. H. Wei, and S. W. Wei, “Step-by-step decoding algorithm
for Reed-Solomon codes,” IEE Proc. Commun., Vol. 147, No. 1, pp. 8-12,
February 2000.
[15] T. C. Chen, C. H. Wei, and S. W. Wei, “A Pipeline Structure for High-
Speed Step-by-Step RS decoding,” IEICE Trans. Commun., Vol. E86-B, No. 2,
February 2003.
[16] R. Le Bidan, C. Leroux, C. Jego, P. Adde, and R. Pyndiah, “Reed-Solomon
Turbo Product Codes for Optical Communications: From Code Optimization to
Decoder Design,” EURASIP Journal on Wireless Communicational and
Networking, vol. 2008, Article ID 658042, 14 pages, 2008.
doi:10.1155/2008/658042
[17] C. S. Yeh, I. S. Reed, and T. K. Truong, “Systolic multipliers for finite
fields GF(2m)” , IEEE Trans. Comput., Vol. C-33, No. 4, pp. 357-360,
April 1984.
[18] C. Jégo, P. Adde, and C. Leroux, “Full-parallel architecture for turbo
decoding of product codes,” Electronics Letters, vol. 42, no. 18, pp.
1052–1054, 2006.
[19] C. Leroux, G. Le Mestre, C. Jégo, P. Adde, and M. Jézéquel, “A 5-Gbps
FPGA prototype of a (31,29)2 Reed-Solomon Turbo Decoder,” 5th
International Symposium on Turbo Codes and Related Topics, Lausanne,
Suisse, pp. 67-72, September 2008.
[20] C. Leroux, C. Jego, P. Adde, and M. Jezequel, “On the higher efficiency
of parallel Reed-Solomon turbo-decoding,” In ICECS’08: 15th
international conference on electronics, circuits and system, 31st August– 3rd September, pp. 1308-1311, 2008.
[21] D. H. Lawrie, “Access and alignment of data in an array processor,” IEEE
Transactions on Computers, vol. C-24, no. 12, pp. 1145-1155, 1975.
[22] 黃憲政, “方塊渦輪碼之探討與效能分析,” 中華大學碩士論文, 2009.[23] 陳昱竹, “渦輪乘積碼解碼演算法之解碼效能與設計複雜度比較,” 國立交通大學碩士論文,2005.
[24] 陳俊良, “干擾環境下應用方塊渦輪碼於跳頻系統之研究,” 中原大學碩士論文, 2004.[25] 李思賢, “渦輪乘積碼與時空區段聯結碼,” 中原大學碩士論文, 2004.[26] 林銀議, 數位通訊原理-編碼與消息理論, 五南圖書, 2005.
[27] S. B. Wicker and V. K. Bhargava, Reed-Solomon Codes and Their
Applications, IEEE Press, New York, 1994.