臺灣博碩士論文加值系統

複晶矽(polysilicon)薄膜電晶體(TFT)技術在面版製造中扮演一個重要的角色，它增進了同時將主動矩陣及周邊驅動電路整合在同一基板上的能力。然而，複晶矽薄膜電晶體導致一些不良效應，像是包括大的關閉狀態(off-state)的電流(leakage current，漏電流)，紐結效應(kink effect)和熱載子效應。 這些效應主要是由於在汲極旁邊的高側向電場所引起。因此，必須降低該電場以改善上述的現象。在本篇論文中，將分析擁有掩埋層通道及輕摻雜結構的新式複晶矽薄膜電晶體。我們將使用TSUPREM-4來模擬薄膜電晶體的結構，並操作MEDICI來模擬元件的電氣特性。
首先，製造三種不同結構的複晶矽薄膜電晶體，他們是：傳統型單一汲極/源極的薄膜電晶體、使用臨界電壓調整方式(Vth-adjustment method)的薄膜電晶體以及掩埋層通道(buried-channel, BC)的薄膜電晶體。其他的製程參數，像是各個閘極氧化層的厚度及不同的閘極長度（或是通道長度）也將與三種結構的電晶體一併討論。再加上輕摻雜結構之後，這三種結構的電晶體也會再討論。
最後，我們比較傳統型單一汲極/源極的薄膜電晶體、使用硼為1E12 cm-2的劑量以及20keV能量的臨界電壓調整方式薄膜電晶體、使用磷為2E11 cm-2的劑量，30keV能量以及使用硼為1E12 cm-2的劑量與20keV能量的掩埋層通道薄膜電晶體，以及擁有磷為2E11 cm-2的劑量，100keV能量輕摻雜結構的掩埋層通道薄膜電晶體的電氣特性。可以發現擁有輕摻雜結構的掩埋層通道薄膜電晶體，比起傳統型單一汲極/源極的薄膜電晶體、使用臨界電壓調整方式的薄膜電晶體以及掩埋層通道的薄膜電晶體，將會擁有更低的漏電流。因為它對藉由陷阱狀態所產生的載子發射機制能更有效的抑制。而且，輕摻雜結構的掩埋層通道薄膜電晶體也有相對較小的側向電場。因此，使用簡單及自我對準方式所製作出的輕摻雜結構掩埋層通道薄膜電晶體，在面板製作方面提供一個有效的方法來改善偏壓引起的問題。

Poly-Si TFTs play an important role for panel fabrications, enhancing the integration of both active matrix and peripheral driving circuitry on the same substrate. However, poly-Si TFTs lead to some poor effects, like large off-state currents, kink effect and hot carrier effect. These effects are mainly due to the high lateral electric field intensity near the drain, so it is necessary to alleviate the electric field intensity for improving those problems mentioned-above. We use TSUPREM-4 to simulate the TFT structures and operate MEDICI to simulate the electrical characteristics of devices.
In this thesis, three types TFTs with different structure were studied. They are the conventional single source/drain TFTs, the TFTs with Vth-adjustment method and the buried-channel (BC) TFTs. Some fabrication parameters such as various gate oxide thicknesses and different gate length (or channel length) would also included in discussion with the three structures. After adding the LDD structure, the samples of the three structures would be also discussed.
Finally, the electrical characteristics of the conventional single source/drain TFTs, the TFTs with Vth-adjustment method, the BC TFTs, and the BC TFTs with LDD structure were compared. They were the conventional single source/drain TFTs, boron implantation dose at 1E12 cm-2 doses with 20keV energy for the TFT with Vth-adjustment method, the BC TFT with phosphorus implantation dose at 2E11 cm-2 doses with 30keV energy and boron implantation dose at 1E12 cm-2 doses with 20keV energy, and the LDD structure is formed with phosphorus implantation dose at 2E11 cm-2 doses at 100 keV energy for the BC TFT. It could be found that the BC TFTs with LDD structure achieve much smaller leakage and less kink effect than the other three structures, attributable to the more effective suppression of carrier emission via trap states. Moreover, the lower lateral electric field intensity near the drain also showed in BC TFTs with LDD structure. As the result, the simple and self-aligned method for the BC with LDD structure is an effective way on panel fabrications to improve some bias-caused problems.

Abstract (Chinese)………………………………………………………i
Abstract (English)………………………………………………………iii
Acknowledgement (Chinese)……………………………………………v
Contents…………………………………………………………………vi
Table List………………………………………………………………viii
Figure Captions…………………………………………………………ix
Chapter 1 Introduction……………………………………………………1
1-1 Application of poly-silicon thin film transistors…………………1
1-2 Introduction of poly-Si TFTs………………………………………1
1-3 Electrical Properties in poly-Si…………………………………3
1-4 Substrate/Channel engineering……………………………………4
1-5 Motivation……….………………………………………………5
1-6 Thesis organization…………………………………………………6
Chapter 2 Device scheme………………………………………………8
Chapter 3 Results and discussion………………………………………14
3-1 Electrical characteristics of the conventional TFTs of undoped poly-Si and that with Vth-adjustment method……………………14
3-1-1 Influence of implantation dose……………………………15
3-1-2 Influence of gate oxide thickness…………………………16
3-1-3 Influence of gate length……………………………………16
3-2 Electrical characteristics of BC TFTs……………………………26
3-2-1 Influence of implantation dose……………………………26
3-2-2 Influence of implantation energy………………………27
3-2-3 Influence of gate oxide thickness…………………………29
3-2-4 Influence of gate length………………………………….29
3-3 Electrical characteristics of TFTs with LDD structure…………48
3-3-1 Influence of LDD structure………………………………48
3-3-2 Influence of gate oxide thickness…………………………50
3-3-3 Influence of gate length…………………………………51
3-4 Electrical characteristics for four structures……………………62
3-4-1 Influence of different structure……………………………62
3-4-2 Influence of gate oxide thickness………………………63
3-4-3 Influence of gate length…………………………………64
Chapter 4 Conclusions……………………………………………………75
Reference………………………………………………………………78

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