臺灣博碩士論文加值系統

本論文提出四種改良式低功率消耗參考電壓電路。第一種電路混合BJT與MOSFET之正負溫度係數以產生輸出參考電壓；第二種電路是以MOSFET的正負溫度係數特性產生零溫度係數參考電壓；第三種則是產生零溫度係數參考電壓，並回授產生電路所需之偏壓電流的低功率參考電壓電路，第四種則將電路中所有MOSFET都偏壓於弱反轉區。四種電路均利用MOS電晶體偏壓於弱反轉區時具有低功率消耗的特性，並適當組合具有正、負溫度係數之電壓以實現具有零溫度係數的低功率消耗之參考電壓。

本論文除了提供詳細工作原理以外，並使用HSPICE電路模擬軟體以0.35微米製程參數執行佈局前、後模擬以及下線製作；電路供應電壓分別是1.7V與1.8V，溫度變化範圍則是從-20°C遞增至120°C，根據模擬結果顯示，當供應電壓1.7V且使用混合電路，溫度為25°C時，輸出電壓約為448.5mV，輸出電壓變化量為0.57mV，消耗功率為24.18μW，PSRR為-64.9dB，溫度係數約為8.34ppm/°C；而當供應電壓1.8V且使用低功率參考電壓電路，溫度為25°C時，輸出電壓約為657mV，輸出電壓變化量為0.23mV，消耗功率為1.03μW，PSRR為-81dB，溫度係數約為2.5ppm/°C。

電路模擬結果與理論推導相符合，可證實本論文所提出之改良式低功率參考電壓電路的可行性。本論文所提出低功率參考電壓電路可適用於各種類比積體電路。

In this thesis, four improved Low-Power Reference Voltage Circuits have been proposed. The first circuit used the positive and negative temperature coefficients of the BJT and MOSFET, respectively, to generate the required reference voltage. The second circuit used the positive and negative temperature coefficients of the MOSFET to reach the zero-temperature coefficient reference voltage. The third circuit generated the zero-temperature coefficient reference voltage first and then feedback to the bias circuit to provide the necessary bias currents. The last circuit kept all MOSFET in the circuit to be biased in the weak inversion region. In all the proposed circuits, MOS transistors are biased in the weak inversion region to achieve the low-power consumption characteristics. After that, with proper combination of the positive and the negative temperature coefficients of voltage, the low-power consumption with zero-temperature coefficient reference voltage can be realized.

Detailed design principles have been disclosed in this thesis, and the HSPICE simulation program with 0.35-μm process parameters have been used to perform the pre/post-layout simulations. Also the proposed circuits have been taped-out with the same process parameters.
The supply voltages of the proposed circuit are 1.7V and 1.8V, respectively. The temperature ranges from -20°C to 120°C. According to the simulation results, when the supply voltage is 1.7V and the temperature is 25°C, the output voltage of the proposed mixed-mode circuit is 448.5mV, the maximum output voltage variation is 0.57mV, the power dissipation is 24.18μW, the corresponding PSRR is -64.9dB, and the temperature coefficient is 8.34ppm/°C. As the supply voltage is 1.8V and the temperature is 25°C, the output voltage of the proposed low-power reference voltage circuit is 657mV, the maximum output voltage variation is 0.23mV, the power dissipation is 1.03μW, the corresponding PSRR is -81dB, and the temperature coefficient is 2.5ppm/°C.

The simulation and measurement results are consistent with the theoretic analysis which can prove the validity of the proposed circuits. The proposed circuit can be further used in various analog circuit applications.

摘要..........i
Abstract..........ii
誌謝..........iv
目錄..........v
表目錄..........vii
圖目錄..........viii
符號說明..........xi
第一章 緒論..........1
1.1 積體電路發展沿革..........1
1.2 設計流程..........2
1.3 研究方向與重點..........4
1.4 論文架構簡介..........4
第二章 能隙參考電壓回顧..........5
2.1 參考電壓介紹..........5
2.2 參考電壓電路架構與工作原理..........5
2.2.1 二極體穩壓電路..........6
2.2.2 BJT參考電壓電路..........8
2.2.3 弱反轉區與MOSFET參考電壓電路..........13
2.3 簡易電流源分析..........17
第三章 混合式參考電壓設計..........19
3.1 混合式參考電壓電路..........19
3.2 電路工作原理..........20
3.3 電路佈局前模擬結果..........22
第四章 低功率參考電壓設計..........24
4.1 低功率參考電壓電路..........24
4.2 第一種改良式參考電壓電路..........24
4.2.1 電路工作原理..........25
4.2.2 電路佈局前模擬結果..........27
4.3 第二種改良式參考電壓電路..........29
4.3.1 電路工作原理..........29
4.3.2 電路佈局前模擬結果..........30
4.4 第三種改良式參考電壓電路..........31
4.4.1 電路工作原理..........31
4.4.2 電路佈局前模擬結果..........32
第五章 模擬與量測結果..........35
5.1 晶片設計流程..........35
5.2 電路模擬結果..........38
5.2.1 混合式參考電壓電路..........38
5.2.2 第一種改良式參考電壓電路..........42
5.2.3 第二種改良式參考電壓電路..........46
5.2.4 第三種改良式參考電壓電路..........50
5.3 電路晶片實現與晶片量測結果..........54
5.3.1 混合式參考電壓電路..........54
5.3.2 改良式低功率參考電壓電路..........58
第六章 結論..........66
參考文獻..........67
Extended Abstract..........70
簡歷(CV)..........74

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