臺灣博碩士論文加值系統

本篇論文描述一個工作在2.4GHz 互補式金氧半導體正交相位壓控震盪器及除頻器，並將這兩個電路應用在非整數除頻頻率合成器中。
在本論文中提出了一個採用全新架構的正交相位壓控震盪器，以台灣積體電路製造股份有限公司以0.25微米製程實現，並自行量測完成。量測結果顯示本架構產生的正交相位訊號可使大部分低鏡像信號架構達到足夠的鏡像頻率拒斥。本論文也提出一個工作電壓1.5伏特雙模除頻器，其中使用四相位注入鎖定除頻器並利用相位切換技巧有效減低功率消耗，工作在2.4~2.5GHz頻帶約消耗7mW功率。
本論文並以delta-sigma非整數除頻頻率合成器來驗證上述兩電路的功能。此頻率合成器包括相位頻率偵測器、傳統電流幫浦、三階濾波器、本文提出的四相位壓控震盪器及雙模除頻器。

A design of 2.4GHz CMOS quadrature VCO and frequency divider and their applications in fractional-N frequency synthesizer is described in this thesis.
The proposed whole new quadrature generator is fabricated using a standard TSMC 0.25um CMOS process and has been measured completely. The measurement results of this chip meet the requirement that provides sufficient image rejection ratio in the most RF receiver architecture. A 1.5v 32/33 dual-modulus frequency divider is also presented in this thesis. It combines quadrature injection-locked frequency divider and phase switching technique to reduce power consumption. It works at frequency band 2.4~2.5GHz and consumes about 7mW.
A delta-sigma fractional-N frequency synthesizer including two blocks mentioned above is presented. This frequency synthesizer combines these two blocks and proves their functionality. This synthesizer introduces conventional deadzone-less PFD, conventional charge-pump, third order loop filter, proposed quadrature VCO, proposed quadrature injection-locked divider combining with phase switching technique and an all digital third order single bit delta-sigma modulator with mash3 delta-sigma modulator dithering input as fractional modulus generator.

CHAPTER 1 INTRODUCTION 1
1.1 BACKGROUND 1
1.2 MOTIVATION 3
1.3 REVIEW ON CMOS FREQUENCY SYNTHESIZER CIRCUITS 3
1.3.1 Synthesizer with quadrature phase output 5
1.3.2 Quadrature phase generator 7
1.3.3 Integer-N & Fractional-N synthesizer 13
1.3.4 Frequency divider in synthesizer 17
1.4 ORGANIZATION OF THIS THESIS 21
CHAPTER 2 QUADRATURE PHASE GENERATOR 22
2.1 DESIGN CONSIDERATIONS 22
2.1.1 Allpass filters 22
2.1.2 Proposed Quadrature phase generator 26
2.1.3 Performance evaluation 30
2.2 CIRCUIT REALIZATION 35
2.3 SIMULATION RESULTS 40
2.4 TESTING CONSIDERATION 45
CHAPTER 3 32/33 DUAL-MODULUS FREQUENCY DIVIDER 47
3.1 CIRCUIT REALIZATION 47
3.1.1 Quadrature injection locked frequency divider 48
3.1.2 Phase-switching circuit 50
3.1.3 True-single-phase-clock D-type Flip-Flop 53
3.1.4 Selection control 54
3.2 LAYOUT AND POST-SIMULATION RESULTS 57
3.2.1 Layout considerations 57
3.2.2 Post-layout-simulation results 58
CHAPTER 4 FRACTIONAL-N SYNTHESIZER 64
4.1 DESIGN CONSIDERATION 64
4.2 CIRCUIT REALIZATION 67
4.2.1 Delta-Sigma modulator 68
4.2.2 Phase Frequency Detector 71
4.2.3 Charge pump 73
4.2.4 Loop filter 74
4.3 SIMULATION RESULTS 75
CHAPTER 5 EXPERIMENTAL RESULTS AND DISCUSSIONS 84
5.1 LAYOUT CONSIDERATION 84
5.2 MEASUREMENT SETUP 87
5.3 EXPERIMENTAL RESULTS 92
CHAPTER 6 CONCLUSIONS AND FUTURE WORKS 101
6.1 CONCLUSIONS 101
6.2 FUTURE WORKS 102

[1] William F. Egan. Frequency synthesis by phase lock. Second edition. New York. Wiley-Interscience.
[2] Behzad Razavi. RF microelectronics. Prentice Hall PTR.
[3] Wei-Zen Chen. “Frequency Synthesis circuits techniques for wireless transceiver.” NCTU Phd thesis, 1998.
[4] Conexant Systems, Inc. Fractional-N synthesizers white paper. Conexant System, Inc. Feb 2001.
[5] Sherif H. Galal, Mohamed S. Tawfik and H. F. Ragaie, “On the Design and Sensitivity of RC Sequence Asymmetric Polyphase Networks in RF Integrated Transceivers,” IEEE International Symposium on Circuits and Systems, Vol.2, pp. 593 -597, 1999
[6] Sherif H. Galal, H. F. Ragaie, and Mohamed S. Tawfik, “RC Sequence Asymmetric Polyphase Networks for RF Integrated Transceivers, ” IEEE Trans on circuits and systems II, vol.47, No.1, pp. 18-27, Jan 2000.
[7] Kare Tais Christensen, “LC Quadrature generation in integrated circuits,” IEEE international symposium on circuits and systems, Vol.1, pp.41-44, 2001.
[8] Michiel Steyaert, Marc Borremans, Johan Janssens, Bram De Muer, Nobuyuki Itoh, Jan Craninckx, Jan Crols, Eiji Morifuji, Hisayo Sasaki Momose, Eilly Sansen, “A single-chip CMOS transceiver for DCS-1800 wireless communication,” IEEE International Solid-State Circuits Conference, pp. 48 -49, 1998
[9] Hamid R.Rategh, Hirad Samavati, and Thomas H. Lee, “A CMOS Frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver,” IEEE Journal of Solid-State Circuits, Vol. 35 Issue.5, pp. 780 —787, May 2000
[10] Hamid R. Rategh, Hirad Samavati, and Thomas H. Lee, “A 5-GHz, 32mW CMOS frequency synthesizer with an injection locked frequency divider,” IEEE Symposium on VLSI Circuits, pp. 113 —116, 1999
[11] Hamid R. Rategh, and Thomas H. Lee, “Super-harmonic injection-locked frequency dividers,” IEEE Journal of Solid-State Circuits, Vol. 34, Issue. 6, pp. 813 —821, June 1999
[12] Hamid R. Rategh, Hirad Samavati, and Thomas H. Lee, “A 5GHz, 1mW CMOS voltage controlled differential injection locked frequency divider,” IEEE Custom Integrated Circuits, pp. 517 —520, 1999
[13] Hamid R. Rategh, and Thomas H. Lee, “Super-harmonic injection-locked oscillators as low power frequency dividers,” IEEE Symposium on VLSI Circuits, pp. 132 —135, 1998.
[14] Jiren Yuan and Christer Svensson, “New Single-clock CMOS latches and flipflops with improved speed and power savings,” IEEE Journal of Solid-State Circuits, Vol. 32, Issue. 1, pp. 62 —69, Jan. 1997
[15] Brian Miller and Robert J. Conley, “A multiple modulator fractional divider,” IEEE Transactions on instrumentation and measurement, Vol. 40, No. 3, pp. 578 —583, Jun 1991
[16] Tom A. D. Riley, Miles A. Copeland, and Tad A. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE journal of Solid State circuits, Vol. 28, No. 5, pp. 553 —559, May 1993
[17] Terrence P. Kenny, Thomas A. D. Riley, Norman M. Filiol, and Miles A. Copeland, “Design and realization of a digital delta-sigma modulator for fractional-N frequency synthesis,” IEEE Transactions on vehicular technology, Vol. 48, No. 2, pp. 510-521, March 1999.
[18] Woogeun Rhee, Bang-Sup Song, and Akbar Ali, “A 1.1GHz CMOS fractional-N frequency synthesizer with a 3-b third-order delta-sigma modulator,” IEEE journal of Solid-State circuits, Vol. 35, No. 10, pp.1453-1460, Oct 2000.