臺灣博碩士論文加值系統

　　鎖相迴路已經是目前不可或缺的重要時脈產生器來源，尤其是在無線通訊收發器中，鎖相迴路被用來當作頻率合成器，合成出不同的頻率時脈與所接受到的高頻信號相乘，進而降頻至基頻進行信號處理，為了因應頻道間距以及通訊品質，頻率合成器的頻率解析度和相位雜訊是時脈設計很重要的考量因素。
　　由於典型的整數型鎖相迴路頻率解析度受限於參考時脈，因此頻率合成器必須使用三角積分鎖相迴路來完成，但其平均的概念伴隨著量化雜訊，許多技術發展出來抑制這些雜訊，其中提高三角積分器的超採樣率，將量化雜訊移至更高頻率被濾波的方法是本論文主要採用的技術。
　　有別於已發表的高超採樣率三角積分鎖相迴路，本論文首先分析除頻器與頻率偵測器之間的離散與連續時間轉換介面，並且為此介面的行為設計了因應的數位有限脈衝響應濾波器在三角積分器的輸出，並且搭配所提出的半整數除頻器，以抑制量化雜訊，並且在特定頻率有更進一步的濾波效果，相較於傳統的三階三角積分鎖相迴路的量化雜訊有21 dB的抑制量。
　　晶片是使用台積電 180 nm CMOS 混合信號製程所設計，頻率合成器頻率範圍為 2.58 GHz 到 3.45 GHz ，核心電路功率消耗約為 12 mW ，量測時搭配 FPGA 板來實現三角積分調變器以及有限脈衝響應濾波器，量測結果驗證了在 1/5 及 3/5 倍參考頻率處有更進一步的濾波效果。

In modern wireless communication systems, frequency synthesizers with high frequency resolution are used to up/downconvert signals to desired bands precisely. Phase-locked loops (PLLs) with the delta-sigma technique are a common way to achieve high frequency resolution. However, quantization noise is inevitable introduced during division ratio dithering, it greatly degrades the out-band noise performance especially in a high-bandwidth phase-locked loop.
We focus on the study of quantization noise suppression. Analysis of quantization noise from delta-sigma modulation and the interface between continuous-time and discrete-time signal processing in PLLs plays an important role in this thesis. Based on this analysis, we propose a high oversampling rate (H-OSR) delta-sigma frequency synthesizer on which an finite-impulse response (FIR) digital filter and a novel half-integer frequency based on the phase compensation technique are embedded.
The simulation result shows that the proposed architecture is able to suppress the quantization noise by 21 dB compared with the conventional MASH 1-1-1 structure. Moreover, the notch filtering effect from the FIR filter can further reduce quantization noise at the specific frequency, and improve the phase jitter performance.
The proposed frequency synthesizer was verified by the silicon results in a TSMC 0.18μm CMOS process. Output frequency range is from 2.58 GHz to 3.45 GHz, the core power consumption is 12 mW. At the frequency of 1/5 and 3/5 reference frequency in the phase noise spectrum, the notch filtering effect can be found. Besides, FPGA is used to implement the delta-sigma modulator and the FIR filter during the measurement.

目錄
ABSTRACT I
中文摘要 II
第一章 緒論 1
1.1 研究動機 1
1.2 論文架構 2
第二章 鎖相迴路基本概念 3
2.1 基本運作原理 3
2.2 鎖相迴路線性化 7
2.3 穩定性及雜訊分析 9
2.3.1穩定性分析 9
2.3.2雜訊分析 12
第三章 超取樣與三角積分技術 17
3.1 技術摘要 17
3.2 量化器與量化雜訊 17
3.3 超取樣技術 19
3.4 三角積分技術 20
3.5 鎖相迴路採用三角積分技術 21
3.6 鎖相迴路內量化雜訊分析 24
第四章 高超取樣率三角積分鎖相迴路 27
4.1 技術發展目的 27
4.2 技術分析與介紹 28
4.3 實現方法回顧 29
4.3.1混合信號分析方法 29
4.3.2直接迴授型 30
4.3.3反混疊濾波型 33
4.3.4標準高超採樣率型 35
4.4 提出的高超取樣率的三角積分鎖相迴路架構 37
第五章 電路設計模擬與量測 42
5.1 建議架構實現概述 42
5.2 三角積分器與數位濾波器 46
5.3 半整數除頻器 48
5.3.1次整數型除頻器實現原理 48
5.3.2實現方法回顧 49
5.3.3提出的半整數除頻器架構 52
5.3.4半整數除頻器電路實現 54
5.4 頻率相位偵測器與電荷泵 59
5.5 壓控振盪器 61
5.6 電路模擬統整 64
5.7 電路量測 68
第六章 結論與改進 76
參考文獻 78

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