臺灣博碩士論文加值系統

本篇論文為設計5.25GHz射頻前端發射機，主要應用於IEEE802.11ac系統，其中電路包含電壓控制振盪器、混頻器和功率放大器，電路中所使用之元件均為TSMC 0.18 m 1P6M CMOS Mixed-Signal模型，並使用國家晶片系統設計中心所提供之Agilent Advanced Design System(ADS)軟體進行電路模擬。
電壓控制振盪器使用電流再利用式架構和轉導提升架構來降低消耗功率，並使用電感互感的方式增加電路Q值和縮小晶片面積。量測結果顯示，可調頻率範圍可達11.7%，在振盪頻率為5.03GHz時，輸出功率為-4.5dBm，相位雜訊在1MHz的偏移頻率時為-110dBc/Hz，性能指標FOMT為-173.7dBc，在供應電壓為1.8V時，消耗功率為15.3mW，晶片面積為0.725#westeur024#0.540mm2。
混頻器使用雙端平衡式架構，在負載級使用共模回授架構來提高轉換增益，並在轉導級使用改良式二級共源極架構來放大中頻訊號。量測結果顯示，在輸出訊號頻率為5.25GHz時，轉換增益為9.11dB，輸入1dB增益壓縮點為-16dBm，輸入三階截止點為-5dBm，LO-RF隔離度為29.3dB，LO-IF隔離度為45.6dB，IF-RF隔離度為113.3dB，在供應電壓為1.8V時，消耗功率為9.54mW，晶片面積為1.209#westeur024#1.421 mm2。
功率放大器整體架構分為兩級，第一級使用電流再利用式架構來降低消耗功率，並使用折疊疊接的架構來提高增益，第二級使用共源極架構來提高輸出功率，並使用線性化偏壓電路來提高線性度。量測結果顯示，在輸出訊號頻率為5.25GHz時，轉換增益為10.248dB，輸出1dB增益壓縮點為6.5dBm，輸出三階截止點為19dBm，功率增加效率為12.8%，在供應電壓為1.8V時，消耗功率為79.7mW，晶片面積為1.291#westeur024#0.857mm2。
射頻前端發射機使用直接升頻式架構來減少被動元件的使用以及減少消耗功率。模擬結果顯示，當輸入中頻訊號頻率為10MHz和本地振盪訊號的頻率為5.24GHz時，輸出射頻訊號為5.25GHz，功率增益為38.543dB，輸出1dB增益壓縮點為14.568dBm，輸入1dB增益壓縮點為-22dBm，輸出三階截止點為40dBm，輸入三階截止點為1.5dBm，在供應電壓為1.8V時，消耗功率為110.52mW。

In this thesis, we design a 5.25GHz RF transmitter front-end, mainly used in IEEE 802.11ac system and composed of a voltage-controlled oscillator, a mixer, and a power amplifier. The circuit components are simulated using TSMC 0.18 um 1P6M CMOS Mixed-Signal model and the Agilent Advanced Design System (ADS) software provided by National Chip Implementation Center.
The voltage controlled oscillator uses current reused architecture and gm boosting technique to reduce power consumption and uses the mutual inductance to increase the circuit Q value and reduce the chip area. Measurement results show that the tuning range is up to 11.7%. When the oscillation frequency is 5.03GHz, the output power is -4.5dBm, the phase noise is -110dBc/Hz at 1MHz offset, the performance indicators FOMT is -173.7dBc. When the supply voltage is 1.8V, the power consumption is 15.3mW and the chip area is 0.725 #westeur024# 0.540mm2.
The mixer is designed with double balanced mixer architecture and common mode feedback architecture for the load level to improve conversion gain. In the transconductance stage, we use a modified two common source architecture to amplify the IF signal. Measurement results show that the output signal frequency is 5.25GHz, the conversion gain is 9.11dB, input 1dB compression point is -16dBm, input third-order intercept point is -5dBm, LO-RF isolation is 29.3dB, LO-IF isolation is 45.6dB, IF-RF isolation is 113.3dB. When the supply voltage is 1.8V, the power consumption is 9.54mW and the chip area is 1.209 #westeur024# 1.421 mm2.
The overall architecture of power amplifier is divided into two stages. The first stage adopts current reused architecture to reduce power consumption, and uses the folded cascode architecture to increase the gain. The second stage uses a common source architecture to increase the output power and the linear bias circuit to improve the linearity. Measurement results show that the output signal frequency is 5.25GHz, the conversion gain is 10.248dB, output 1dB compression point is 6.5dBm, output third-order intercept point is 19dBm, power added efficiency is 12.8%. When the supply voltage is 1.8V, the power consumption is 79.7mW and the chip area is 1.291 #westeur024# 0.857mm2.
The RF transmitter front-end is designed with direct up-conversion architecture to reduce passive components and power consumption. Simulation results show that when the input IF signal frequency is 10MHz and local oscillator signal frequency is 5.24GHz, the output RF signal is 5.25GHz, power gain is 38.543dB, output 1dB compression point is 14.568dBm, input 1dB compression point is -22dBm, output third-order intercept point is 40dBm, input third-order intercept point is 1.5dBm. When the supply voltage is 1.8V, the power consumption is 110.52mW.

摘要.......................................................I
Abstract..................................................II
目錄......................................................IV
圖目錄.....................................................VI
表目錄.....................................................IX
第一章 緒論.................................................1
1.1 IEEE802.11 ac系統介紹.................................1
1.2 研究動機..............................................2
1.3 射頻發射機架構介紹......................................3
1.4 論文架構..............................................4
第二章 電壓控制振盪器.........................................5
2.1 電壓控制振盪器簡介......................................5
2.2 電壓控制振盪器原理......................................5
2.2.1 回授分析法....................................5
2.2.2 負電阻分析法...................................7
2.2.3 環形振盪器....................................8
2.2.4 LC諧振振盪器..................................9
2.3 電壓控制振盪器重要參數.................................12
2.3.1 相位雜訊.....................................12
2.3.2 可調頻率範圍..................................18
2.3.3 輸出功率.....................................19
2.3.4 消耗功率.....................................19
2.4 5.5GHz電壓控制振盪器設計...............................19
2.4.1 電路架構.....................................19
2.4.2 模擬結果.....................................23
2.4.4 量測結果.............................................34
2.4.3 結論........................................36
第三章 混頻器...............................................37
3.1 混頻器簡介...........................................37
3.2 混頻器原理...........................................37
3.3 混頻器架構...........................................39
3.3.1 被動式混頻器..................................39
3.3.1 主動式混頻器..................................40
3.4 混頻器重要參數........................................42
3.4.1 轉換增益.....................................43
3.4.2 三階交互調變失真..............................43
3.4.3 隔離度.......................................45
3.5 5.25GHz混頻器設計....................................46
3.5.1 電路架構.....................................46
3.5.2 模擬結果.....................................49
3.5.3 量測結果.....................................60
3.5.4 結論........................................65
第四章 功率放大器...........................................66
4.1 功率放大器簡介........................................66
4.2 功率放大器原理與架構...................................66
4.2.1 放大模式功率放大器.............................66
4.2.2 切換式功率放大器..............................68
4.3 功率放大器重要參數.....................................68
4.3.1 1dB增益壓縮點................................69
4.3.2 穩定度.......................................69
4.3.3 效率........................................71
4.4 5.25GHz功率放大器設計.................................71
4.4.1 電路架構.....................................71
4.4.2 模擬結果.....................................74
4.4.3 量測結果.....................................87
4.4.4 結論........................................90
第五章 應用於IEEE802.11 ac發射機模擬.........................91
5.1 發射機電路架構........................................91
5.2 發射機模擬結果........................................91
5.3 結論..................................................96
第六章 總結與未來展望........................................97
參考文獻...................................................98

[1]IEEE Standard for Information technology Telecommunications and information exchange between systems Local and metropolitan area networks Specific requirements, The Institute of Electrical and Electronics Engineers, 2013.
[2]http://www.ithome.com.tw/node/75919
[3]張盛富, 張家展, 無線通訊射頻晶片模組設計-射頻系統篇. 全華圖書, 2011.
[4]Behzad Razavi, Design of Analog CMOS Integrated Circuits. McGrawHill, 2011.
[5]江衍忠, 射頻基頻電路設計RFIC Design. 國立中興大學, 2007.
[6]柯鈞林, Design of RF CMOS IC. 國家晶片系統設計中心, 2011.
[7]Ali Hajimiri, and Thomas H. Lee, “A General Theory of Phase Noise in Electrical Oscillators,” IEEE Journal of Solid State Circuits, Vol. 33, No. 2, pp. 174-194, 1998.
[8]賴永齡, 王岳華, 謝孟翰, 王弘毅, 高頻通訊電路設計, 微波積體電路設計， 教育部顧問式通訊科技人才培育計畫, 2007.
[9]Thomas H Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press, 1998.
[10]Yi-Pei Su, Wei-Vi Hu, Jia-Wei Lin, Yun-Chung Chen, Sakir Sezer, and Sao-Jie Chen, “Low Power Gm-Boosted Differential Colpitts VCO,” IEEE International SOC Conference (SOCC), 2011.
[11]Joonhong Park, Junyoung Park, Youngwan Choi, Kweebo Sim, and Donghyun Baek, “A Fully-Differential Complementary Hartley VCO in 0.18 um CMOS Technology,” IEEE Microwave and Wireless Components Letters, Vol. 20, No. 2, pp. 91-93, 2010.
[12]Tai Nghia Nguyen, and Jong-Wook Lee, “Low Phase Noise Differential Vackar VCO in 0.18 um CMOS Technology,” IEEE Microwave and Wireless Components Letters, Vol. 20, No. 2, pp. 88-90, 2010.
[13]Jian-An Hou, and Yeong-Her Wang, “A 5 GHz Differential Colpitts CMOS VCO Using the Bottom PMOS Cross-Coupled Current Source,” IEEE Microwave and Wireless Components Letters, Vol. 19, No. 6, pp. 401-403, 2009.
[14]Young-Jin Moon, Yong-Seong Roh, Chan-Young Jeong, and Changsik Yoo, “A 4.39–5.26 GHz LC-Tank CMOS Voltage-Controlled Oscillator with Small VCO-Gain Variation,” IEEE Microwave and Wireless Components Letters, Vol. 19, No. 8,pp. 524-526, 2009.
[15]Behzad Razavi, RF Microelectronics, Prentice Hall, 1998.
[16]張盛富, 張家展, 無線通訊射頻晶片模組設計-射頻晶片篇. 全華圖書, 2011.
[17]Chih-Hao Chen, Pei-Yuan Chiang, and Christina. F. Jou, “A Low Voltage Mixer with Improved Noise Figure,” IEEE Microwave and Wireless Components Letters, Vol.19, No.2, pp. 92-94, 2008.
[18]C. -C. Meng, T. -H. Wu, J. -S. Syu, S. -W. Yu, K. -C. Tsung, and Y. -H. Teng, “2.4/5.7-GHz CMOS Dual-Band Low-IF Architecture Weaver Hartley Image Rejection Techniques, “IEEE Transactions on Microwave Theory and Techniques, Vol. 57, No. 3, pp. 552-561, 2009.
[19]S.A.Z Murad, M.F Ahmad, M. Mazalan, M.M Shahimin, S.A.A Rais, and M.N Norizan, “A Design of 5.2 GHz CMOS Up-Conversion Mixer with IF Input Active Balun,” IEEE Symposium on Wireless Technology and Applications, 2011.
[20]Jong-Ha Kim, Hee-Woo An, and Tae-Yeoul Yun, “A Low-Noise WLAN Mixer Using Switched Biasing Technique,” IEEE Microwave and Wireless Components Letters, Vol. 19, No. 10, pp. 650-652, 2009.
[21]Cheng-Chi Yen, and Huey-Ru Chuang, “A 0.25um 20dBm 2.4GHz CMOS Power Amplifier with an Integrated Diode Linearizer,” IEEE Microwave and Wireless Components Letters, Vol. 13, No. 2, pp. 109-111, 2003.
[22]S. H. L. Tu, and S. C. H. Chen, “5.25 GHz CMOS cascode power amplifier for 802.11a wireless local area network,” IET Microwave Antennas and Propagation, Vol. 2, No. 6, pp. 627-634, 2008.
[23]Afsahi. A, Behzad. A, Magoon. V, and Larson. L. E, “Linearized Dual-Band Power Amplifiers with Integrated Baluns in 65 nm CMOS for a 2 2 802.11n MIMO WLAN SOC,” IEEE Journal of Solid State Circuit, Vol. 45, No. 5, pp. 955-966, 2010.
[24]Peter Haldi, Debopriyo Chowdhury, Patrick Reynaert, Gang Liu, and Ali M. Niknejad, “A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS,” IEEE Journal of Solid State Circuits, Vol. 43, No. 5, pp. 1054-1063, 2008.
[25]J. Carls, F. Ellinger, U. Joerges and M. Krcmar, “Highly Efficient CMOS C-Band Class-F Power Amplifier for Low Supply Voltages,” Electronics Letters, Vol. 45, No. 24, pp. 1240-1241, 2009.