臺灣博碩士論文加值系統

中文摘要 近年來，隨著可攜式產品，如筆記型電腦、數位相機、手機等的普及，非揮發性記憶體在半導體記憶元件的發展與研究上，其所扮演的角色是愈來愈重要。隨著半導體製程技術逐年的進步，非揮發性記憶體，從最早的唯讀記憶體(Read-Only-Memory，ROM)、可程式唯讀記憶體(Programmable-Read-Only-Memory，PROM)，到可抹除程式化唯讀記憶體(Erasable- Programmable-Read-Only-Memory)、電性可抹除程化唯讀記憶體(Electrically Erasable Programmable Read Only Memory，EEPROM)，以至目前最熱門的快閃記憶體(Flash Memory)，都可看見半導體製程技術在非揮發性記憶體上的運用亦逐年在進步。 本篇論文以一新型單電晶體非揮發性記憶元件為研究主題，實驗並分析其元件特性。此元件利用通道熱載子作為起寫入機制，成功驗證其可讀寫的特性，此外，並針對其可靠度進行更深入的分析。就此記憶元件而言，不論在元件耐久度、資料持久度或是讀取/寫入/抹除特性上，與現今各式非揮發性記憶元件相比之下，皆有優異的表現。

Abstract
Non-Volatile Memories (NVMs) have been developed and
progressing in past decades, and recently it has been received much
attention in mobile and portable applications, such as mobile phones,
smart cards and digital cameras. In the First part of this thesis, the history
of the Non-Volatile Memory (NVM) and the concept of the NVM are
introduced. And the typical NVMs, such as EPROM, EEPROM, and flash
memory are also introduced.
The main purpose of this thesis presents the characteristics of a
single-polysilicon non-volatile memory (NVM) device by using a novel
NOI n-MOSFETs. Hot carriers are generated in NOI devices and to be
stored as memories . The characteristics of this potential single-transistor
NVM cell, including 2-bit operation, programming and erasing
characteristics, are investigated. Their stability and reliability
characteristics such as retention and cycling are also evaluated.

Contents
中文摘要 ...…………………………………………………………….Ⅰ
Abstract ................................................................................................. Ⅱ
Acknowledgments ................................................................................. Ⅲ
Contents ................................................................................................. Ⅳ
Figure captions ...................................................................................... Ⅵ
Table captions ........................................................................................ Ⅹ
章節摘要
第一章 非揮發性記憶體之回顧 ………………………………... XI
第二章 高電場效應於非揮發性記憶體上之應用 ..................... XII
第三章 新型非揮發性快閃記憶體之量測結果與特性分析...... XIII 第四章 總結與未來展望 …………………………………........ XVI
Chapter 1 An Overview of Non-Volatile Memory .............................. 1
1-1 Introduction of Non Volatile Memory (NVM) ......................... 1
1-2 Floating Gate Memory Device ……………………………….. 8
1-3 Charge Trapped Memory Device ……………………………. 15
1-4 Development Trends ………………………………………… 18
Chapter 2 High Field Operations in NVMs ………………………... 21
2-1 Introduction ………………………………………………….. 21
2-2 Hot Carrier Injection (HCI) ………………………………….. 22
2-3 Band-To-Band Tunneling (BTBT) …………………………... 31
2-4 Fowler-Nordheim (FN) Tunneling …………………………... 33
2-5 Summary …………………………………………………….. 37
V
Chapter 3 Characteristics Analysis of Novel NOI Devices ………... 39
3-1 The Fabrication of NOI Devices …………………………….. 40
3-2 Operation of the NOI Devices ……………………………….. 43
3-2-1 Programming ……………………………………….... 44
3-2-2 Erasing ……………………………………………….. 45
3-2-3 Reading ………………………………………………. 46
3-3 Characterizations of NOI Devices …………………………… 50
3-4 Reliability Evaluation ………………………………………... 55
3-4-1 Endurance ……………………………………………. 55
3-4-2 Data Retention ……………………………………….. 56
3-5 Lateral Profiling of Interface Traps and Oxide Charge in NOI
MOSFET Devices ……………………………………………. 57
3-6 Summary …………………………………………………….. 62
Chapter 4 Conclusions and Future Prospectives …………………... 65
4-1 Conclusions ………………………………………………….. 65
4-2 Future Prospectives ………………………………………….. 66
Reference ……………………………………………………………... 68
VITA ………………………………………………………………….. 76
VI
Figure captions
Figure 1-1: The Semiconductor Memory Tree.
Figure 1-2: The history of nonvolatile memory (NVM).
Figure 1-3: Charge trapped in N-channel memory device
Figure 1-4: (a) Electron potential diagram of NVMs for cases in the “0”
(erased) state and in “1” (programmed) state. (b) The device
threshold voltage is shifted when the charge trapped in the floating gate (or the charge trapping material).
Figure 1-5: The cross section of “Floating Gate device”, it contains two
stacked gates; the bottom gate surrounded by dielectric
material and used to store connect charges is called “Floating
Gate”. The top gate used to supplying the operating bias is
called “Control Gate”.
Figure 1-6: The structure of charge-trapping device. High deep-level trap
density dielectrics are used to capture charges such as Si3N4 or Al2O3.
Figure 1-7: The structure of the MIMIS device
Figure 1-8: The schematic cross section of FAMOS during programming
shows the formation of the depletion region and the region
nears the drain where the avalanche occurs.
Figure 1-9: The EPROM is programmed by CHE and UV light erase.
Figure 1-10: (a) The schematic cross section of EEPROM includes one
select transistor and one floating gate transistor. (b) FN
tunneling is the program and erase mechanism of EEPROM.
Figure 1-11: The structure of the ETOX device
VII
Figure 1-12: (a) The schematic cell array, layout view, and cross section
of the NAND architecture. (b) The schematic cell array, layout view, and cross section of the NOR architecture.
Figure 1-13 : The cross section of “charge trapping device”，it uses high
deep-level trap density material (such as Si3N4 and Al2O3)
to save charge.
Figure 1-14: The schematic cross section of SONOS.
Figure 1-15: The schematic cross section of Twin MONOS.
Figure 2-1: (a) The Hot-Carrier Effect generation and (b) lateral electric
field versus distance between source and drain, showing the
high field region at the drain junction.
Figure 2-2: Substrate and gate currents as a function of gate voltage for
n-MOS at a constant high drain bias.
Figure 2-3: The mechanisms of hot carriers inject into oxide.
Figure 2-4: Schematic for drain avalanche hot-carrier injection
mechanisms.
Figure 2-5: Schematic and energy band diagram for CHE and CHISEL injection mechanisms.
Figure 2-6: Schematic representation of the substrate hot electrons
Figure 2-7: Schematic representation of the location of oxide traps and
interface states generated by CHE injection Figure 2-8: A deep-depletion region is formed in the gate-drain overlap
region.
Figure 2-9: The voltage drop in the deep-depletion layer becomes so large
that various transporting mechanisms become possible.
VIII
Figure 2-10: The energy band diagram for once a positive bias is applied to the gate and electrons transport through the triangular Si /
SiO2 potential barrier from the Si conduction band into SiO2
conduction band. The voltage drop in the deep-depletion
layer becomes so large that various transporting mechanisms become possible.
Figure 2-11: For ultra-thin oxide (40 Å), electrons can directly tunnel ≦
through the forbidden energy gap of the SiO2 layer from the
inverted silicon surface to the gate without entering the oxide
conduction band.
Figure 3-1: The schematic process flow of the NOI NVM device.
Figure 3-2: The simulated doping profile underneath the SiN spacer in
NOE device
Figure 3-3: The schematic cross section of that the NOE NVM device
uses the CHEI as the programming mechanism. Figure 3-4: The schematic cross section of that the NOE NVM device
uses the BTBT hot hole injection as the erasing mechanism.
Figure 3-5: The 2-bit operation schemes of the NOI n-MOSFET. Figure 3-6: The schematic cross section of forward read bit-1 of the NOE
NVM device, and electrons can travel through the trapped
charge region easily as increasing the drain voltage.
Figure 3-7: The schematic cross section of reverse read bit-1 of the NOE
NVM device.
Figure 3-8: The ID-VG comparison between the standard and NOI
n-MOSFETs.
Figure 3-9: The VD vs. Vth of NOI device.
IX
Figure 3-10: The ID-VG the NOI implanted non-volatile memory devices.
State (I) indicates both bit-1 and bit-2 are programmed, i.e.
(0,0); State (II) indicates bit-1 programmed and bit-2 erased,
i.e. (0,1). State (III) indicates both bit-1 and bit-2 both are
programmed then return to the erased state, i.e. (1,1).
Figure 3-11: (a) The programming characteristics and (b) The erasing
characteristics of NOI MOSFET
Figure 3-12: The cycled-endurance characteristic of NOE MOSFET. Figure 3-13: The data retention characteristic of NOI MOSFET. Figure 3-14: Experimental setup for single junction charge-pumping
technique.
Figure 3-15: Charge pumping curves measured before and after stress for
the purpose of directly profiling the hot-carrier damage.
Figure 3-16. Lateral profiles of (a) interface traps and (b) oxide charge near the drain junction, transformed from the three charge
pumping curves in Figure 3-15.

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