臺灣博碩士論文加值系統

本論文設計一個具電路效能最佳化，應用於音頻上的超取樣類比數位轉換器。此一轉換器採用三角積分調變(Delta Sigma Modulation)技術，相較於其他轉換器架構，能達到較高的解析度同時對類比電路的規格要求也較低，並且也僅需要較少電路與功耗。
本論文將詳述此一超取樣轉換器的核心，亦即全差動兩階類比/數位三角積分調變器電路。在電路的設計上，先以行為模擬工具MATLAB設計系統架構，接著再以由上而下的設計方式，逐一計算出類比元件諸如開關尺寸、最小輸入、電容大小、運算放大器及量化器各項電路規格的最佳值，以達成最佳化的目的。
此一三角積分調變器電路採用TSMC 0.18μm 1P6M 製程來設計。取樣頻率設定為6.4MHz、超取樣率為128，輸入訊號為 -3 dB時，行為模擬訊號雜訊比(SNR)可達92 dB，相當於有效位元數15位元。電路模擬訊號雜訊比可達89 dB，其解析度相當於15位元。

This thesis implements an oversampling analog to digital converter(ADC), applied for audio applications, with optimized design on overall circuits. This ADC, using delta sigma modulation technique, can achieve higher resolution with relaxed requirement on analog circuit specifications and less circuit power consumption, compared with other types of ADCs.
This thesis presents the design of the core of the ADC, the second-order fully differential delta sigma modulator circuits, in detail. The modulator architecture is designed by behavioral simulation tool, MATLAB, next from a top-down design approach is adopted to determine the optimized values of analog circuits such as switch sizes, minimal input capacitor values, and operational amplifier and quantizer specifications.
The AD modulator is designed with TSMC 0.18μm single-poly six-metal process. With sampling frequency of 6.4MHz, oversampling rate of 128, input amplitude of -3 dB of the full swing, the signal to noise ratio (SNR) is simulated as 92 dB from behavioral simulations and as 89 dB from the circuit simulations. Both are equivalent to 15 bits for resolution.

Abstract i
摘要 ii
目錄 iii
圖目錄 v
表目錄 viii
第一章　緒論 1
第一節　前言 1
第二節　研究動機 4
第三節　論文架構 5
第二章　三角積分(ΣΔ)調變原理 6
第一節　取樣速率與解析度的關係 6
第二節　超取樣技術 8
第三節　量化誤差 10
第四節　三角積分調變 13
第三章　電路設計 18
第一節　二階調變器架構設計 18
第二節　抗雜訊交換電容積分器設計 21
壹　運算放大器 23
貳　共模回授電路 25
參　類比開關 26
第三節　量化器與比較器 29
壹　架構介紹 30
貳　比較器 30
第四節　非重疊時脈產生器 32
第五節　設計流程 34
第四章　系統電路模擬結果 35
第一節　運算放大器 35
第二節　比較器與量化器 39
第三節　非重疊時脈產生器 44
第四節　系統電路模擬結果 46
第五章　結論 51
參考文獻 52
作者簡介 57

[1]林當清， “使高解析度低功率消耗之超取樣sigma-delta類比數位轉換器”國立臺灣海洋大學電機工程學系碩士論文， 2004。
[2]A. Marques, V. Peluso, M. Steyaert and W. Sansen, “Optimal parameter for delta-sigma modulator topologies,” IEEE Transactions on Circuits Systems: II, vol. 45, no. 9, pp. 1232-1241, 1998.
[3]A. Rusu and S. Lungu, “Modeling and simulation of low-power and low-voltage delta-sigma modulators,” The 8th IEEE International Conference on Electronics, Circuits and Systems. vol. 1, no. 2-5, pp. 297-300, 2001.
[4]Robert W. Adams “Design and implementation of an audio 18-bit analog to digital converter using oversampling techniques,” Journal of the Audio engineering Society, vol. 34, no. 3, pp. 153-166, 1986.
[5]B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc., 2001.
[6]B. Y. Kamath, R. G. Meyer and P. R. Gray, “Relationship between frequency response and settling time of operational amplifiers,” IEEE Journal of Solid-State Circuits, vol. 9, no. 6, pp. 347-352, 1974.
[7]C. H. Su and K. S. Chao, “A fourth-order cascaded sigma-delta modulator with digital to analog converter error cancellation technique,” The 2002 45th Midwest Symposium on Circuits and Systems, vol. 2, pp. 5-8, 2002.
[8]D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1997.
[9]D. Senderowicz, S. F. Dreyer, J. H. Huggins, C. F. Rahim and C. A. Laber, “A family of differential NMOS analog circuits for a PCM codec filter chip,” IEEE Journal of Solid-State Circuits, vol. 17, no. 6, pp. 1014-1023, 1982.
[10]D. Senderowicz, G. Nicollini, S. Pernici, A. Nagari, P. Confalonieri and C. Dallavalle “ Low-voltage double-sampled ∆Σ converters,” IEEE Journal of Solid-State Circuits, vol. 32, no. 12, pp. 1907-1919, 1997.
[11]D. R. Welland, B. P. Del Signore, E. J. Swanson, T. Tanaka, K. Hamashita, S. Hara and K. Takasuka, “A stereo 16-bit delta-sigma A/D converter for digital audio,” Journal of the Audio engineering Society, vol. 37, no. 6, pp. 476-486, 1989.
[12]F. Medeiro, B. Pérez-Verdú, J. M. de la. Rosa and A. Rodríguez-Vázquez “Fourth-order cascade SC ∆Σ modulators: a comparative study,” IEEE Transactions on Circuits Systems: I, vol. 45, no. 10, pp. 1041-1051, 1998.
[13]G. M. Yin, F. O. Eynde and W. Sansen “A high-speed CMOS comparator with 8-bit resolution ” IEEE Journal of Solid-State Circuits, vol. 27, no. 2, pp. 208-211, 1992.
[14]H. Inose, Y. Yasuda and J. Murakami, “A Telemetering System by Code Modulation -∆Σ Modulation,” IRE Transactions on Space Electronics and Telemetry, vol. 8, no. 3, pp. 204-209, 1962.
[15]J. Silva, U. Moon, J. Steensgaard and G. C. Temes, “Wideband low-distortion delta-sigma ADC topology,” Electronics Letters, vol. 37, no. 12, pp. 737-738, 2001.
[16]K. Vleugels, S. Rabii and B. A. Wooley, “A 2.5-V sigma-delta modulator for broadband communication applications ” IEEE Journal of Solid-State Circuits, vol. 36, no. 12, pp. 1887-1889, 2001.
[17]K. Y. Nam, S. M. Lee, D. K. Su and B. A. Wooley, “A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion,” IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1855-1864, 2005.
[18]L. Williams and B. Wooley, “Third-order sigma-delta modulator with extended dynamic range,” IEEE Journal of Solid-State Circuits, vol. 29, no. 3, pp. 193-202, 1994.
[19]L. Yao, M. S. J. Steyaert and W. Sansen, "A 1-V 140-μW 88-dB audio sigma-delta modulator in 90-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 39, no. 11, pp. 1809-1818, 2004.
[20]M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching Properties of MOS Transistors,” IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433-1440, 1989.
[21]M. R. Miller and C. S. Petrie, “A multibit sigma-delta ADC for multimode receivers ” IEEE Journal of Solid-State Circuits, vol. 38, pp. 475-482, 2003.
[22]M. Safi-Harb and G. W. Roberts, “Low power delta-sigma modulator for ADSL application in a low-voltage CMOS technology,” IEEE Trans. Circuits and Systems: I, vol. 52, no. 10, pp. 2075-2088, 2005.
[23]M. Sarhang-Nejad and G. C. Temes, "A high-resolution multi bit ΣΔ ADC with digital correction and relaxed amplifier requirements," IEEE Journal of Solid-State Circuits, vol. 28, no. 6, pp. 648-660, 1993.
[24]O. Nys and R. K. Hendersin, “A 19-bit low-power multi-bit sigma-delta ADC based on data weighted averaging ” IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp. 933-942, 1997.
[25]P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato and A. Baschirotto, “Behavioral modeling of switched-capacitor sigma-delta modulators,” IEEE Trans. Circuits Systems: I, vol. 50, no. 3, pp. 352-364, 2003.
[26]P. M. Aziz, H. V. Sorensen, and J. Vnder Spiegel, "An overview of sigma-delta converters," IEEE Signal Processing Magazine, vol. 13, no. 1, pp. 61-84, 1996.
[27]R. Schreier and G. C. Temes, Understanding Delta-Sigma Data converters, IEEE Press, John Wiley & Sons, Inc., 2005
[28]S. Haykin, Communication System, 3rd ed., John Wiley & Sons , New York, 1994
[29]S. R. Norsworthy, R. Schreier and G. C. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation, Wiley-IEEE Press, 1997.
[30]W. Schweber, Electronic Communication Systems, Prentice-Hill, Inc., 4th ed., 2002.
[31]W. Wolf, Modern VLSI Design: System-on-Chip Design, Prentice Hall PTR, Inc., 2002.
[32]Y. Fujimoto, P. L. Ré and M. Miyamoto, “A delta-sigma modulator for a 1-bit digital switching amplifier,” IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1865-1871, 2005.
[33]Y. Geerts, A. M. Marques, M. S. J. Steyaert and W. Sansen, “A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1MHz for ADSL applications,” IEEE Journal of Solid-State Circuits, vol. 34, no. 7, pp. 927-936, 1999.
[34]Y. L. Guillou, “Analyzing sigma-delta ADCs in deep-submicron CMOS technologies,” RF Design Magazine, pp. 18-26, 2005.