跳到主要內容

臺灣博碩士論文加值系統

(216.73.216.141) 您好!臺灣時間:2026/07/25 13:30
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:林信太
研究生(外文):Shin-Ta Lin
論文名稱:操作於弱反轉層場效電晶體之極低功率損耗與極小面積CMOS參考電壓之設計與實現
論文名稱(外文):The Design and Implementation of an Ultra Low Power and Small Area CMOS Voltage Reference Based on MOSFET Operated in Weak Inversion Region
指導教授:闕河鳴闕河鳴引用關係
指導教授(外文):Herming Chiueh
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程系所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:96
語文別:中文
論文頁數:78
中文關鍵詞:參考電壓弱反轉層溫度
外文關鍵詞:Voltage ReferenceWeak Inversion RegionTemperature
相關次數:
  • 被引用被引用:1
  • 點閱點閱:696
  • 評分評分:
  • 下載下載:59
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文使用0.18微米互補式金氧半標準製程設計並實現一個與溫度無關的穩定參考電壓源。最近幾年電池供應的系統越來越廣泛使用,隨著這個趨勢,在設計電路時都要求小面積、低功率、高效能,而很多類比電路都會需要一個穩定的參考電壓,因此本論文設計一個低功率與小面積的參考電壓去運用在電池供應的系統中。本電路工作在弱反轉區可用來取代傳統電路中的雙極性電晶體去實現與溫度無關的參考電壓,其功率消耗只有幾百奈瓦且面積只有幾百平方微米。另外,溫度範圍也可以從-80℃到165℃,而其電壓誤差也僅有幾十毫伏特。因此,本設計可以運用在電池供應的系統去供應一個穩定的參考電壓。
This thesis uses standard CMOS 0.18μm process technique to design and realize a stable voltage reference which does not change with temperature. In the recent years, battery-operated systems are used extensively. Along with this tendency, we demand low-power, small-area, and high performance when designing circuits. Many analog circuits need a stable voltage reference, so the thesis shows a low-power and small-area voltage reference to apply in battery-operated systems. Proposed circuits work in weak inverse region to replace the bipolar devices in conventional circuit and using proposed circuits realize CMOS voltage reference which does not change with temperature. Its power consumption only has several hundred nano-Watt and its area is only several hundred squre nanometer. In addition, the voltage derivation only has several dozens milli-Volt when temperature range is from -80℃ to 165℃. Therefore, proposed architectures can supply a stable voltage reference in battery-operated systems.
CONTENTS
Chinese Abstract
English Abstract
Acknowledgements
Contents
Chapter 1 Introduction.....................................1
1.1 Overview of Battery-Operated System.....................................................1
1.2 Motivation..........................................................................3
1.3 Organization........................................................................4
Chapter 2 Review of Voltage Reference……………………5
2.1 Background...........................................................................5
2.2 Conventional Bandgap Reference.....................................................7
2.2.1 Bandgap Reference...................................................................8
2.2.2 BJT and MOS Comparison..............................................................9
2.3 CMOS Voltage References..............................................................10
2.3.1 Voltage Mode of VPTAT and VCTAT....................................................12
2.3.2 Current Mode of VPTAT and VCTAT....................................................15
2.3.3 Voltage Reference Uses Parallel Voltages........................................17
2.3.4 Zero Temperature Coefficient Point (ZTC)…..................................19
2.3.5 Voltage Reference Uses Non-standard Process................................20
2.3.6 Comparison of Voltage Reference......................22
2.3.7 Summary…………………………………………………………..25
Chapter 3 Circuitry Architecture…………………………26
3.1 Design Process…………………….…………………………………..26
3.1.1 Reference Paper………..…………………………………………..26
3.1.2 VPTAT (Proportional to Absolute Temperature)..……………27
3.2 All NMOSFET Voltage Reference (ANVR)…….………………………31
3.2.1 Principle of ANVR.……………………………………………...31
3.2.2 Derivation of ANVR…...………………………………………….32
3.2.3 Post-Layout Simulation of ANVR………………………………34
3.2.4 Discussion of ANVR………………………………………………39
3.3 NMOSFET and PMOSFET Voltage Reference (NPVR)……………40
3.3.1 Principle of NPVR………………………………………………...40
3.3.2 Derivation of NPVR….………………………………………….41
3.3.3 Post-Layout Simulation of NPVR.………………………………44
3.3.4 Discussion of NPVR………………………………………………49
3.4 NMOSFET PMOSFET and Capacitor Voltage Reference (NPCVR)…50
3.4.1 Start-up Circuit of NPCVR…...…………………………………...50
3.4.2 Power Supply Reject Ratio (PSRR)……………………………….51
3.4.3 Post-Layout Simulation of NPCVR….……………………………53
3.4.4 Discussion of NPCVR……………………………………………57
3.5 Comparison……………………………………………………………….58
3.6 Summary………………………………………………………………….60
Chapter 4 Measurement…………………………………...61
4.1 Measurement Set-up……………………………………………………..61
4.2 Experimental Result………………………………………………………63
4.2.1 Experimental Result of ANVR…………………………………...63
4.2.2 Experimental Result of NPVR…………………………………...66
4.2.3 Discussion of ANVR and NPVR………………………………..69
4.2.4 Comparison of ANVR and NPVR…..…………………………..70
4.3 Summary………………………………………………………………….72
Chapter 5 Conclusion and Future Works..……………….73
5.1 Conclusion………………………………………………………………...73
5.2 Future Works……………………………………………………………...74
References…………………………………………………….75
[1]
S. S. Prasad, P. Mandal, “A CMOS beta multiplier voltage reference with improved temperature performance and silicon tenability,” Proceedings of 17th International Conference on VLSI Design, Page(s):551 – 556, 2003.
[2]
D. C. Ferreira, T. C. Pimenta, “A CMOS Voltage Reference Based on Threshold Voltage for Ultra Low-Voltage and Ultra Low-Power,” The 17th International Conference on Microelectronics 2005, Page(s):10 – 12, Dec. 2005.
[3]
M. H. Cheng, Z. W. Wu, “Low-power low-voltage reference using peaking current mirror circuit,” Electronics Letters Volume 41, Issue 10, 12 Page(s):572 – 573, May 2005.
[4]
G. D. Vita, G. Iannaccone, “A Sub-1 V, 10 ppm/°C, Nanopower Voltage Reference Generator,” ESSCIRC Proceedings of the 32nd European Page(s):307 – 310, Sept. 2006.
[5]
I. Nissinen, J. Kostamovaara, “A low voltage CMOS constant current-voltage reference circuit,” ISCAS Proceedings of the 2004 International Symposium on Volume 1, Page(s):I-381 - I-384 Vol.1, May 2004.
[6]
C. P. Liu, H. P. Huang, “A CMOS Voltage Reference with Temperature Sensor using Self-PTAT Current Compensation,” IEEE International SOC Conference, Proceedings, 25-28 Page(s):37 – 42, Sept. 2005.
[7]
M. Danaie, R. Lotfi, “A low-voltage high-PSRR CMOS PTAT & constant-gm reference circuit,” 48th Midwest Symposium on Circuits and Systems Page(s):1807 - 1810 Vol 2, Aug. 2005.
[8]
S. Miller, L. MacEachern, “A nanowatt bandgap voltage reference for ultra-low power applications,” Proceedings of IEEE International Symposium on Circuit and System, Page(s):4, May 2006.
[9]
G. Giustolisi, G. Palumbo, M. Criscione, F. Cutri, “A low-voltage low-power voltage reference based on subthreshold MOSFETs,” IEEE Journal of Solid-State Circuits, Volume 38, Issue 1, Page(s):151 – 154, Jan. 2003.
[10]
P. H. Huang, H. Lin, Y. T. Lin, “A Simple Subthreshold CMOS Voltage Reference Circuit With Channel- Length Modulation Compensation,” Circuits and Systems II: Express Briefs, IEEE Transactions on [see also Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on] Volume 53, Issue 9, Page(s):882 – 885, Sept. 2006.
[11]
T. Ytterdal, “CMOS bandgap voltage reference circuit for supply voltages down to 0.6 V,” Electronics Letters Volume 39, Issue 20, Page(s):1427 – 1428, Oct. 2003.
[12]
Q. A. Khan, D. Dutta, “A programmable CMOS bandgap voltage reference circuit using current conveyor,” Proceedings of the 2003 10th IEEE International Conference on Circuit and System, Volume 1, Page(s):8 - 11 Vol.1, Dec. 2003.
[13]
Yamu Hu; M. Sawan, “A 900 mV 25 uW high PSRR CMOS voltage reference dedicated to implantable micro-devices,” Proceedings of the 2003 International Symposium on Circuits and Systems, Volume 1, Page(s):I-373 - I-376 vol.1, May 2003.
[14]
T. Matsuda, R. Minami, A. Kanamori, H. Iwata, T. Ohzone, S. Yamamoto, T. Ihara, S. Nakajima, “A VDD and temperature independent CMOS voltage reference circuit,” Proceedings of the ASP-DAC Design Automation Conference, Asia and South Pacific Page(s):559 – 560, Jan. 2004.
[15]
F. Bedeschi, E. Bonizzoni, A. Fantini, C. Resta, G. Torelli, “A low-power low-voltage MOSFET-only voltage reference,” Proceedings of the 2004 International Symposium on Circuits and Systems, Volume 1, Page(s):I-57 - I-60 Vol.1, May 2004.
[16]
A. Aldokhaiel, A. Yamazaki, M. Ismail, “A sub-1 volt CMOS bandgap voltage reference based on body-driven technique,” The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, Page(s):5 – 8, June 2004.
[17]
J. Wang, X. Lai, Y. Li, J. Zhang, X. Guo, “A novel low-voltage low-power CMOS voltage reference based on subthreshold MOSFETs,” 6th International Conference On ASIC, Volume 1, Page(s):369 – 373, Oct. 2005.
[18]
R. M. Weng, X. R. Hsu; Y. F. Kuo, “A 1.8- V High-Precision Compensated CMOS Bandgap Reference,” IEEE Conference on Electron Devices and Solid-State Circuits, Page(s):271 – 273, Dec. 2005.
[19]
D. Naro, G. Lombardo, C. Paolino, G. Lullo, “A Low-Power Fully-MOSFET Voltage Reference Generator for 90 nm CMOS Technology,” 2006 IEEE International Conference on Integrated Circuit Design and Technology, Page(s):1 – 4, May 2006.
[20]
H. Lin, D. K. Chang, “A Low-Voltage Process Corner Insensitive Subthreshold CMOS Voltage Reference Circuit,” 2006 IEEE International Conference on Integrated Circuit Design and Technology, Page(s):1 – 4, May 2006.
[21]
K. N. Leung, P. K. T. Mok, “A CMOS Voltage Reference Based On Weighted △Vgs For CMOS Low-Dropout Linear Regulators,” IEEE Journal of Solid-State Circuits, Volume 38, Issue 1, Page(s):146 – 150, Jan. 2003.
[22]
Y. Dai, D. T. Comer, D. J. Comer, C. S. Petrie, “Threshold voltage based CMOS voltage reference,” IEE Proceedings on Circuits, Devices and Systems, Volume 151, Issue 1, Page(s):58 – 62, Feb. 2004.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top