臺灣博碩士論文加值系統

在本論文的第一部份我們提出了一個可產生相位可調之數位化時脈(clock)電路，其具有防止多重閂鎖(multi-locking)之負延遲電路，基本原理為利用柱型移位暫存器及電壓可調式延遲單元來調整需要的負延遲相位。本設計使用TSMC 0.35μm CMOS 1P4M製程。因為採用單擊鎖相技術，因此可縮短鎖定時間，模擬結果與理論值誤差在6%以內。
論文第二個部分中我們描述了一個應用於DVB-T的10位元，80 MHz取樣頻率的類比數位轉換器。此ADC採用的是四通道的平行導管式ADC，並且使用動態比較器跟切換電容式的取值電路來降低功率消耗。在TSMC 0.35um 2P4M製程下的模擬結果SFDR有56dB，有效位元數為9.01位元。

The first topic of this thesis proposes a digital negative phase shifter circuit which generates a clock with adjustable negative delays (phase shift) in order to avoid multi-locking hazards. Arbitrary negative phase can be generated by using multiplexers and voltage variable delay cells to select the required phase shift. The proposed design is implemented by 0.35 um CMOS 1P4M technology. A single-shot locking method is adopted to reduce the locking time. Most important of all, the negative phase shifter is predictable and adjustable. The simulation results show that the accuracy of the proposed design is better than 6%.
The second topic is to describe a 10-bit, 80 MS/s analog-to-digital converter (ADC) for digital video broadcasting over terrestrial (DVB-T) receivers. The ADC is based on a four-channel parallel pipeline architecture which employs dynamic comparators and switch-capacitance sample-and-hold circuit to achieve high speed operation and low power consumption. Simulation results using a TSMC 0.35um 2P4M process show that the proposed ADC achieves 56dB spurious-free dynamic range (SFDR) and 9.01-bit ENOB.

摘要 i
Abstract ii
第一章 簡介 1
1.1 前言 1
1.2 文獻探討 3
1.2.1 負相位時脈產生器 3
1.2.2 類比數位轉換器 5
1.3 論文大綱 6
第二章 相位可調之單擊鎖定負相位時脈產生器 7
2.1 簡介 7
2.2 電路架構與原理說明 8
2.2.1 負延遲clock之動作原理 8
2.2.2 負延遲相位估計 10
2.2.3 各單元架構說明 12
2.3 模擬結果 15
2.3.1 可調式輸入延遲單元 15
2.3.2 整體電路模擬結果 18
2.3.3 理論與模擬結果值比較圖 22
2.3.4 晶片照相圖 22
2.4 量測結果與討論 24
第三章 應用於DVB-T系統之十位元80 MHz類比數位轉換器 30
3.1 簡介 30
3.2 電路架構與原理說明 31
3.2.1 S/H電路 33
3.2.2 1.5-bit ADC stage電路 34
3.2.3 錯誤更正電路 37
3.2.4 四相位時脈電路 38
3.2.5 不重疊(nonoverlaping)時脈電路 41
3.2.6 穩壓電路 41
3.2.7 運算放大器規格考量 43
3.2.8 timing分析 43
3.3 模擬結果　 44
3.3.1 輸出波形 44
3.3.2 DNL/INL 45
3.3.3 SFDR 46
3.3.4 規格列表 47
3.3.5 效能比較 47
3.3.6 佈局考量 48
3.3.7 佈局圖 49
第四章 結論與成果 51

參考文獻 53

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