臺灣博碩士論文加值系統

本論文研究商用雷達頻段接收機之前端CMOS MMICs，設計電路包括：24 GHz低雜訊放大器、混頻器、K-Band壓控振盪器、以及整合低雜訊放大器和混頻器之前端接收電路。晶片皆使用台灣積體電路製造公司(TSMC)的CMOS 0.18 μm製程，其優點為低成本、高良率以及高整合性，是現今RF高頻射頻電路主要製程之一。
低雜訊放大器使用並聯諧振電流再利用的技術，使RF信號在不增加額外功率消耗下二次放大，具有高增益與低功率消耗的特性。模擬結果顯示，在24 GHz增益為11.7 dB、雜訊指數為5.7 dB、功率消耗為6.08 mW。量測結果在18 GHz時增益為11.8 dB、雜訊指數為10.7 dB、功率消耗為6.27 mW，晶片尺寸為0.89 × 0.55 mm2，與模擬結果比較有頻偏的現象。
在混頻器的部分採用了Bulk-Injection的技術，相較於傳統的CMOS Gilbert混頻器降低電壓與功率消耗，整合RF轉導級與LO開關級於一個電晶體並消除寄生效應，模擬結果顯示，最高轉換增益在24 GHz為11.69 dB、雜訊指數為11.92 dB、操作電壓為1.1 V、功率消耗為6.23 mW、輸入三階截斷點為-14 dBm。量測結果顯示，最高轉換增益在22 GHz為 3.81 dB、雜訊指數為19.36 dB、操作電壓為1.1 V、功率消耗為6.16 mW、輸入三階截斷點為-5 dBm，晶片尺寸為0.78 × 0.64 mm2。
壓控振盪器的部分採用考畢茲振盪器作為電路主體，在輸出緩衝電路採用一電感與一電容的Bias-Tee電路提高相位雜訊的特性，模擬結果顯示在振盪中心頻率為22 GHz時，相位雜訊偏移中心頻率1 MHz為-110 dBc/Hz、操作電壓1.5 V時功率消耗(包含緩衝器)為30.88 mW、可調範圍為3.31%，晶片尺寸為0.64 × 0.66 mm2。
最後為整合放大器與混頻器之前端接收電路，混頻器採用Bulk-Injection的技術，放大器採用的單輸入差動輸出的形式，模擬結果顯示，最高轉換增益在24 GHz為21.12 dB、雜訊指數為5.75 dB、功率消耗為14.27 mW，晶片尺寸為1.01 × 0.67 mm2。

致　　謝 i
摘　　要 ii
Abstract iv
目　　錄 vi
圖目錄 viii
表目錄 xi
第一章 緒論 1
1.1 研究背景與動機 1
1.2 CMOS簡介 1
1.3 章節簡述 2
第二章 射頻系統概論 4
2.1 射頻前端接收機 4
2.2 射頻放大器基礎理論 4
2.2.1 散射參數 (S-Parameter) 5
2.2.2 雜訊指數 (Noise Figure) 6
2.2.3 線性度 (Linearity) 8
2.2.4 穩定度 (Stability) 12
2.3 混頻器基礎理論 13
2.3.1 轉換增益 (Conversion Gain) 13
2.3.2 雜訊指數 (Noise Figure, NF) 14
2.3.3 隔離度 (Isolation) 15
2.4 壓控振盪器基礎理論 16
2.4.1 相位雜訊 16
2.4.2 LC振盪器 16
2.4.3 壓控振盪器重要規格 17
2.5 射頻積體電路 18
2.5.1 射頻積體電路之應用與發展 18
2.5.2 量測考量 18
第三章 應用於24 GHz低功耗之低雜訊放大器 22
3.1 電路設計 22
3.2 Shunt-Resonating Current-Reused架構分析 23
3.3 輸入匹配電路分析 24
3.4 模擬與量測結果 25
3.5 結果與討論 30
第四章 應用於24 GHz之混頻器 32
4.1 電路設計 32
4.2 主動負載 (Active Load) 35
4.3 Bulk-Injection分析 35
4.4 模擬與量測結果 36
4.5 結果與討論 41
第五章 應用於K-Band之壓控振盪器 42
5.1 電路設計 42
5.2 振盪器 43
5.3 中央抽頭電感 44
5.4 緩衝器 45
5.5 模擬結果 46
5.6 結果與討論 48
第六章 應用於24 GHz之前端接收電路 51
6.1 前端電路設計 51
6.2 模擬結果 53
6.3 結果與討論 60
第七章 總結 63
參考文獻 65

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