臺灣博碩士論文加值系統

本論文提出設計一個符合成本效益的10位元影像類比前端電路(Analog Front-End；AFE)，包括使用了 256 個 CMOS 影像感測器以及使用數個10位元管線式類比數位轉換器(ADC),取決於所使用的架構。在CMOS影像感測器架構中，主動式CMOS影像感測器是最受歡迎的一種架構，相較於被動式CMOS影像感測器而言，主動式CMOS影像感測器有較高的靈敏度、更低的功耗、以及高整合度。在另一方面，使用管線式類比數位轉換器能達到更高速度的信號處理，如影像中的解析度。
本論文比較三種的CMOS影像類比前端電路(AFE)架構，從這三種電路架構中以取得最好的結果，經過Hspice的模擬結果比較後可知，採用 TSMC 0.18微米、1P/6M、混合信號/射頻、1.8V/3.3V製程資料，以CMOS影像感測器 64 4 + 10 bit ADC 4電路可以得到最佳的面積和功耗的結果，整體電路在64MHz的取樣頻率以及19.53125KHz輸入頻率下SFDR為50dB，晶片總面積為4.381mm ，其消耗功率為312mA。總之在速度的提升，縮小電路面積，電源電壓的降低，功率消耗率的降低將是未來研究發展的主要方向。

This thesis presents design of a 10-bit CMOS image sensor analog front-end (AFE) circuit. The front-end circuit consists of a photodiode array of 256, a three-time sening amplification circuit for each photodiode, and a 10-bit pipelined analog-to-digital converter (ADC) as readout circuit.
Among the CMOS image sensor architectures, the active type is the most popular compared to the passive one. The active CMOS image sensors has higher sensitivity, lower power consumption, and is highly integrated. In addition, use of the pipelined ADC can achieve moderate resolution for higher speed applications such as image processing.
This thesis compares three kinds of CMOS image AFE circuits to obtain the best architecture among them. The TSMC 0.18 um, 1P/6M, mixed-signal/RF, 1.8V/3.3V process is used for design. HSPICE simulation results show that, the architecture with a CMOS image sensor array of 64 by 4 and four 10-bit pipelined ADCs has the best result for area and power consumption. With a sampling frequency of 64MHz and input frequency of 19.53125KHz and the SFDR is 50dB and the power consumption is 312mA. The total chip area is estimated to be 4.381mm . The future work is to enhance the speed, to reduce the circuit area, the supply voltage, and the power consumption.

Abstract-------------------------------------------------------i
摘要-----------------------------------------------------------ii
目錄----------------------------------------------------------iii
圖目錄----------------------------------------------------------v
表目錄---------------------------------------------------------vii
第一章　導論-----------------------------------------------------1
第一節　簡介-------------------------------------------------1
第二節　論文動機----------------------------------------------2
第三節　論文架構----------------------------------------------2
第二章　C M O S 和 CCD影像感測器的介紹 ------------------------3
第一節　CMOS 和 CCD影像感測器的差異結構-------------------------3
第二節　CMOS影像感測器的原理和架構說明--------------------------6
第三章　管線式類比數位轉換器架構介紹--------------------------------10
第一節　取樣保持電路------------------------------------------11
第二節　子類比數位轉換器---------------------------------------12
第三節　1.5位元快閃式類比數位轉換器-----------------------------13
第四節　十位元類比數位轉換電路模擬結果---------------------------14
第四章　CMOS影像感測器電路設計--------------------------------------16
第一節　CMOS影像感測器電路-------------------------------------16
第二節　CMOS影像感測器電路的三種組合-----------------------------21
第五章　CMOS影像感測器類比前端電路設計與模擬---------------------------29
第一節　CMOS影像感測器和10位元類比數位轉換電路三種組合--------------29
第二節　比較各CMOS影像感測器和10位元類比數位轉換電路三種組合所產生的面積和功耗-------36
第六章 結論 -----------------------------------------------------40
參考文獻-----------------------------------------------------------41
作者簡介-----------------------------------------------------------44

[1]國家晶片系統設計中心電子報第115期，2010。
[2]劉憲駿， “100MHz 10位元類比數位轉換器之設計” ，國立交通大學電機與控制工程學系碩士論文，2003。
[3]B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Inc., 2001.
[4]Bo Xia, A. Valdes-Garcia and E. Sanchez-Sinencio, “A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver,” IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 530-539, 2006.
[5]H. Van de Vel, B. Buter, H. van der Ploeg, M. Vertregt, G. Geelen and E. Paulus, “A 1.2V 250mW 14b 100MS/s digitally calibrated pipeline ADC in 90nm CMOS,” IEEE Symposium on VLSI Circuits, pp. 74-75, 2008.
[6]C. C. Lee and M. P. Flynn, “A 12b 50MS/s 3.5mW SAR assisted 2-stage pipeline ADC,” 2010 IEEE Symposium on VLSI Circuits, pp. 239-240, 2010.
[7]D. Johns and K. Martin., Analog Integrated Circuit Design, John Wiley & Sons, Inc., 1997.
[8]Hui Liu and Marwan Hassoum, “A 9-b 40-MSample/s reconfigurable pipeline analog-to-digital converter,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 7, pp. 449-456, 2002.
[9] J. Oliverira, J. Goes, M. Figueiredo, E. Santin , J. Fernandes and J. Ferreira, “An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 57, no. 2, pp. 105-109, 2010.


[10] L. Picolli, P. Malcovati, L. Crespi, F. Chaahoub and A. Baschirotto, “A 90nm 8b 120Ms/s-250Ms/s pipeline ADC,”34th European Solid-State Circuits Conference, pp. 266-269, 2008.
[11] L. Sumanen, M. Waltari and K. A. I. Halonen, “A 10-bit 200MS/s CMOS parallel pipeline A/D converter,” IEEE Journal of Solid-State Circuits, vol. 36, no. 7, 2001.
[12] M. K. Hati and T. K. Bhattacharyya, “Design of low power parallel pipeline ADC in 180nm standard CMOS process,” 2011 International Conference on Communications and Signal Processing, pp.9-13, 2011.
[13] S. M. Jamal, D. Fu, N. C.-J. Chang, P. J. Hurst and S. H. Lewis, “A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration,” IEEE Journal of Solid State Circuits, vol. 37, no. 12, pp. 1618-1627, 2002.
[14] R. Jacob Baker, W. Li Harry and E. Boyce David, CMOS Circuit Design, Layout, and Simulation, second edition, John Wiley & Sons，2004.
[15] S. Mathur, M. Das, P. Tadeparthy, S. Ray, S. Mukherjee and B. L. Dinakaran, “A 115mW 12-Bit 50 MSPS pipelined ADC,” IEEE International Symposium on Circuits and Systems, vol. 1, pp. 913-916, 2002.
[16] S. Roy, S. K. Dey and S. Banerjee, “A parallel pipeline ADC with a sub-ADC employing an improvized dynamic comparator,” 2009 IEEE Region 10 Conference, pp. 1-6, 2009.
[17] T. N. Andersen , B. Hernes, A. Briskemyr, F. Telsto, J. Bjornsen, T. E. Bonnerud and O. Moldsvor, “A cost-efficient high-speed 12-bit pipeline ADC in 0.18-um digital CMOS,” IEEE Journal of Solid-State Circuits, vol. 40, no. 7, pp. 1506-1513, 2005.
[18] Tingting Chen, Zheying Li, Bo Li, Yuemei Li, Chunlei Wang and Jianjian Wang, “Improved power scaling issue for pipeline ADC,” International Symposium on Intelligent Signal Processing and Communication Systems, pp. 454-457, 2007.
[19] Young-Ju Kim, Hee-Cheol Choi, Si-Wook Yoo, Seung-Hoon Lee, Dae-Young Chung, Kyoung-Ho Moon, Ho-Jim Park and Jae-Whui Kim, “A re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, low-power 10b 0.13um CMOS pipeline ADC,” IEEE Custom Integrated Circuits Conference, pp. 185-188, 2007.
[20] Yun Chiu, P. R. Gray and B. Nikolic, “A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR,” IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2139-2151, 2004.
[21] Zhuang Zhaodong and Li Zhiqun, “A 7-bit 16MS/s low-power CMOS pipeline ADC,” 2011 IEEE 13th International Conference on Communication Technology, pp. 1082-1085, 2011.
[22] CICeNEWS Sep 15th,2007 volume 83應用導向之運算放大器設計 (Application-Specific OPAMP Optimization with NeoCircuit）, 王建中。
[23] Design of Analog CMOS Integrated Circuits By Behzad Razavi,2000.
[24] CMOS電路模擬與設計 鐘文耀 鄭美珠 編著，2003。