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研究生:蘇榮焜
研究生(外文):Su, Jung-Kun
論文名稱:工作於1 kHz至10 MHz並具有良好抗雜訊能力的一位元量化全數位式鎖相迴路
論文名稱(外文):An One-Bit Quantized ADPLL with 1 kHz to 10 MHz Capture Range and Strong Noise Immunity
指導教授:高銘盛
指導教授(外文):Kao, Ming-Seng
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電信工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2010
畢業學年度:99
語文別:英文
論文頁數:52
中文關鍵詞:鎖相迴路全數位式鎖相迴路
外文關鍵詞:phase-locked loopPLLADPLL
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在本論文中,我們嘗試設計一個應用於1 kHz至10 MHz的通用型一位元量化全數位式鎖相迴路。本電路主要應用於馬達、電力輸出設備以及其他工作於該頻段的電路或系統。由於超寬頻的鎖相迴路實現上很困難,因此我們提出一種方法能夠有效鎖定未知頻率的信號。同時,我們希望本電路能適應各種工作環境,因此所提出的架構具有良好的抗雜訊能力。
在所提的架構中,我們將鎖定程序分為兩個部份:捕獲程序與追蹤程序。捕獲程序利用二分法來搜尋可能的頻率範圍;追蹤程序負責修正微小的頻率差異並補償相位誤差。由模擬結果顯示,本架構在SNR=0 dB的環境下都能具有良好的表現,成功完成一個同時具備超寬捕獲範圍及良好抗雜訊能力的全數位式鎖相迴路。

In this thesis, we would like to design a universal one-bit all digital phase-locked loop (ADPLL) which can be applied in the frequency range from 1 kHz to 10 MHz. The applications of this circuit include motor control, power supply design and other applications that work in the specified frequency range. We propose an efficient and reliable scheme to lock the unknown input signal within the ultra-wide frequency region. Moreover, the proposed scheme has strong noise immunity, which can work well in serious noisy environment.
We divide the locking process into two parts: Acquisition Process and Tracking Process. We use the binary search to search the possible region of the input frequency in the acquisition process. We further use the tracking process to remove the frequency difference and compensate the phase error. According to our simulation results, the proposed scheme has superior performance for the designed frequency range even when SNR = 0 dB.

Chapter 1 Introduction 1
1.1 PLL Overview 1
1.2 Motivation 3
1.3 Thesis Organization 4
Chapter 2 One-Bit Quantized ADPLL System Overview 5
2.1 Operating Principle of Traditional PLL 5
2.1.1 Phase-Locked Loop Basics 5
2.1.2 Linear PLL 7
2.1.3 Digital PLL 8
2.1.4 All-Digital PLL 9
2.1.5 Comparison 10
2.2 Operating Principle of One-Bit Quantized ADPLL 12
2.2.1 One-Bit Quantized ADPLL Basics 12
2.2.2 One-Bit Quantized Phase Detector 13
2.2.3 Frequency Estimation 16
2.2.4 One-Bit Quantized ADPLL 20
2.3 Summary 25
Chapter 3 The Proposal System 26
3.1 Design Challenge 26
3.2 Acquisition Process 28
3.3 Tracking Process 37
3.4 Summary 39
Chapter 4 Simulation Results 40
4.1 Noiseless Environment 40
4.2 Noise Environment 46
4.3 Summary 49
Chapter 5 Conclusions 50
Reference 52

[1] G.. C. Hsieh; J. C. Hung, “Phase-locked loop techniques. A survey” IEEE Trans. Ind. Electron. Vol.43 609-615, 1996
[2] R. E. Best, Phase-Locked Loops: Design, Simulation, and Application, 5th ed., McGraw-Hill, New York, 2003.
[3] D. H. Wolaver, Phase-Locked Loop Circuit Design, Prentice Hall, New Jersey, 1991.
[4] F. M. Gardner, Phaselock Techniques, 3rd ed., John Wiley & Sons, New York, 2005.
[5] Y. S. Choi; H.H. Choi; T. H. Kwon, “An adaptive bandwidth phase locked loop with locking status indicator”, Science and Technology 2005 KORUS 2005 Proceedings, pp.826-829, 2005
[6] C.C. Chung, C. Y. Lee, “An all-digital phase-locked loop for high speed clock generation”, IEEE Solid-State Circuits Society, Vol. 38 347-351, 2003
[7] P. L. Chen, C. C. Chung, C. Y. Lee, “An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications,” IEEE Circuits and Systems, Vol. 5 4875 – 4878, 2005
[8] C. F. Chang, M. S. Kao, “High accuracy carrier phase discriminator in one-bit quantized software-defined receiver” IEEE Signal Processing Letter, Vol.15 397-400, 2008
[9] C. F. Chang, R. M. Yang and M. S. Kao, “Implementation of an innovative phase discriminator for improved tracking performance in one-bit software GPS receiver”, ION NTM, 2008
[10] H. T. Lee, “One-bit quantized phase-locked loop with ultra-wide capture range”, a master thesis in NCTU CM, 2009

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