臺灣博碩士論文加值系統

本論文提出了一個在多層高速數位印刷電路板使用四分之一波長開路殘段共振器抑制電源線在2.4GHz與5GHz的射頻干擾，本文所提出的濾波器結構為四層板的印刷電路板，使用以下的方案可讓雜訊減少，四分之一波長開路殘段共振器為佈在第三層的帶線結構，藉由在四分之一波長開路殘段共振器的連通柱四周加入四個接地連通柱，可以抑制電磁(Electromagnetics, EM)輻射、平面腔體的共振以及插入損耗(|S21|)的峰值雜訊，電場的分布圖說明了平面腔體共振是如何的影響本論文所提出的結構的插入損失。本文所提出的濾波器結構對於時域的接地彈跳雜訊，以及電源線上與共振器中心頻率相同或是相近的電源雜訊也能有顯著的降低。最後在模擬以及測量中有著相似的表現，結果闡明了本文所提出的濾波器結構對於降低雜訊有著良好的性能。

This work proposes low noise generation radiofrequency interference (RFI) noise suppression filter for a power trace that is based on a quarter-wavelength open-stub resonator (QWOSR) in a multilayered high-speed digital PCB (printed circuit board). RFI noise with frequencies at 2.4GHz and 5GHz is considered. The proposed filter structure is a four-layer PCB. The low noise generation includes the following schemes. The trace of the QWOSR is a stripline on the third layer. Four ground vias are added adjacent to the QWOSR via, which is short. Electromagnetic (EM) radiation noise, plan cavity resonance, ground bounce noise (GBN), and peak noise on insertion loss (|S21|) are all reduced. The electric field distributions are elucidated to understand how the effect of cavity resonance on the insertion loss (|S21|) values of the proposed filter structure. The proposed filter structure significantly reduces the time-domain ground bounce and power noise whose frequency is equal or close to the center frequency of filter. Finally, favorable comparisons between simulated and measured results confirm the excellent low noise generation performance of the proposed filter structure.

目錄
摘要 I
Abstract II
致謝 III
目錄 V
圖目錄 VI
表目錄 VIII
第一章 簡介 1
1-1研究動機 1
1-2文獻回顧與探討 1
1-3 章節概要 2
1-4 成果貢獻 2
第二章 四分之一波長共振濾波器 3
2-1共振濾波器原理 3
2-2在多層印刷電路板結構中的問題 5
第三章 平面雜訊效應 7
3-1平行平面共振效應對插入損失的影響 7
3-2接地彈跳雜訊效應 14
第四章 平面雜訊抑制 17
根據上一章節的結果，四分之一波長開路殘段共振器的連通柱愈短除了有良好的插入損耗曲線之外所形成的接地彈跳雜訊也愈少，所以以下分析我們將選用連通柱最短的CASE1來做模擬分析。 17
4-1幾何結構參數分析 17
4-2時域雜訊抑制 23
第五章 實驗驗證 26
第六章 結論 31
參考文獻 32

圖目錄
圖2-1 (A)結構A (B)結構B (C)結構C (D)結構D為微帶線電源線加入四分之一波長開路殘段共振器之側視圖。(E)結構A (F)結構B (G)結構C (H)結構D的俯視圖。 4
圖2-2 結構A~結構D共振器共振頻率在2.4GHZ的(A)插入損耗|S21| (B)三公尺電場輻射；結構A~結構D共振器共振頻率在5GHZ的(C) 插入損耗|S21| (D)三公尺電場輻射 6
圖3-1 各種提出微帶線(電源線)結構加四分之一波長開路殘段共振器的側視圖，(A-1)CASE1加四個接地連通柱；(A-2)CASE1無四個接地連通柱；(B-1)CASE2加四個接地連通柱；(B-2)CASE2無四個接地連通柱；(C-1)CASE3加四個接地連通柱；(C-2)CASE3無四個接地連通柱 8
圖3-2 比較電源線加入四分之一波長開路殘段共振器模擬|S21|的結果 10
圖3-3 (A)比較各種平行平面大小結構模擬的|S11|結果 (B)比較各種平行平面大小且無四個額外接地連通柱的電源線加入四分之一波長開路殘段共振器結構模擬的|S21|結果 12
圖3-4 比較兩種結構((A-1)與(A-2))兩平行平面在幾乎同樣的共振頻率的電場分布((B-1)(B-2)~1.4GHZ；(C-1)(C-2)~1.6GHZ；(D-1)(D-2)~1.95GHZ；(E-1)(E-2)~4.65GHZ；(F-1)(F-2)~5.2GHZ；(G-1)(G-2)~6.1GHZ；(H-1)(H-2)~6.75GHZ)) 13
圖3-5 比較三種測試結構(CASE1、CASE2、CASE3)有/無加入四個接地連通柱共振頻率在(B) 2.4GHZ與(C) 5GHZ時的模擬時域接地彈跳雜訊(VGB)波型 15
圖3-6 比較三種測試結構(CASE1、CASE2、CASE3)加上槽線以及有/無加入額外接地連通柱的結果，並觀察在共振頻率(D) 2.4GHZ與(C) 5GHZ下的耦合雜訊(VCN) 16
圖4-1 比較了我們所提出共振點分別在(A)2.4GHZ與(B)5GHZ的濾波器結構加入不同距離(LGV)的額外接地連通柱|S21|的模擬結果 18
圖4-2 比較提出結構共振點分別在(A)(B)2.4GHZ與(C)(D)5GHZ並加入不同距離(LGV)額外接地連通柱的模擬時域接地彈跳雜訊(VGB)以及頻域的耦合雜訊(VCN) 20
圖4-3 比較提出共振點分別在(A)2.4GHZ與(B)5GHZ的濾波器結構加入不同半徑大小(RGV)的額外接地連通柱|S21|的模擬結果 21
圖4-4 比較提出共振點分別在(A)2.4GHZ與(B)5GHZ的不同共振器寬度(WR)的濾波器結構|S21|的模擬結果 22
圖4-5 (A)提出的濾波器結構的俯視圖(四分之一波長開路殘段共振器在左側)，(B)~(E)比較了雜訊(VNS)在提出結構共振頻率為2.4GHZ與5GHZ之時域波型的結果(VTDT) 25
圖5-1 所有六種實驗板的實際照片((A) MB 1, (B) MB 2, (C)MB 3, (D) MB 4, (E) MB 5, (F) MB 6). 27
圖5-2 顯示了提出的濾波器結構(A)有/(B)無加入額外四個接地連通柱的模擬以及量測|S21| 28
圖5-3 顯示了提出的濾波器結構(A)有/(B)無加入額外四個接地連通柱的模擬以及量測|S31|(耦合雜訊) 29
圖5-4 (A)使用向量網路分析儀以及電流探棒量測實驗結構(B)比較模擬以及量測的|S21|參數 30

表目錄
表2-1 幾何結構尺寸及其材料特性 4
表3-1 三個基本測試結構的幾何尺寸 8
表5-1 幾何結構尺寸及其材料特性 27

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