臺灣博碩士論文加值系統

In this thesis, a 1×2 3-D on-chip optical path using silicon waveguides and 45° micro-mirrors is proposed for optical interconnect splitters. The benefits of a 3-D structure are explored by comparing related studies and discussing their usefulness.

The design of straight 3-D silicon trapezoidal waveguide using 45° micro-mirrors is discussed and verified by ray tracing software. The optical characteristics of this straight 3-D silicon trapezoidal waveguide structure are simulated, which includes the coupling efficiency of the straight 3-D silicon trapezoidal waveguide structure with a multi-mode fiber (MMF) at the receiving end of the structure, for waveguide upper-widths ranging from 35 ~ 75 μm. The coupling efficiency between the 3-D straight waveguide structure and the MMF ranges from 52.4% for 35 μm down to 36.8% for 75 μm case.

The alignment tolerance of the structure to the input light source from a single-mode fiber (SMF) is simulated by finding the center of the waveguide input port and then shifting the input light source along both x and z axis with intervals of 5 μm and calculating the coupled power between the straight waveguide structure and the MMF. The 1-dB alignment tolerance of a straight waveguide with an upper-width of 50 μm structure for the x-axis ranges from -39 ~ 29 μm and for the z-axis has a range from -13.6 ~ 12.6 μm.

The design of the proposed 1×2 3-D on-chip optical path using silicon waveguides and 45° micro-mirrors is introduced and discussed next. The design and the optical pathway of this 3-D splitter waveguide structure are studied for a range of input upper-waveguide widths ranging from 35 ~ 75 μm. The coupling efficiency of each of the two output ports of the splitter waveguide structure with MMF are calculated, this would represent the amount of optical power that can be transmitted by each output. The coupling efficiency for the output through the splitter structure of the waveguide referred to as optical path 1 (OP1) ranges from 8.65% for waveguide upper-width of 35 μm to 27.6% for waveguide upper-widths 75 μm. While for the output of optical path 2 (OP2) which transmits the light not deflected by the splitter junction, the coupling efficiency between the output and the MMF ranges from 48% for waveguide upper-width of 35 μm to 30.3% for waveguide upper-widths of 75 μm.

The fabrication of the trapezoidal silicon waveguides with 45° micro-mirrors used for the proposed 1×2 3-D on-chip optical path is detailed including the formation of the hard mask layer by dry etching process and formation of the trapezoidal silicon waveguide structure, followed by polishing of the substrate and coating of insulation layer by Chemical Vapor Deposition (CVD). Optical Microscopy and Scanning Electron Microscopy are used to check the results from fabrication.

The optical performance of both the fabricated straight and 1×2 splitter 3-D on-chip optical paths are measured using an input light source from SMF and a MMF at the receiving end of the waveguide. Results from simulation and measurement of show that this structure can achieve close to 1:1 power ratio when the waveguide upper-width is at 70 μm with coupling efficiency at 8%.

在論文中，我們提出一個光學連接器的模組，使用矽基波導傳輸，並搭配45度反射面擷取部分光源，達到一分為二分光器的效果。再來將與最近的研究做比較以討論此三維結構的優點與實際的應用層面。在結構的尺寸中，我們先使用光線追跡模擬軟體模擬判斷其結構在不同尺寸下的光耦合效率。
首先模擬的是尚未分光的長直波導，其設計的結構為梯形長直波導。此梯形波導的頂寬設計由35 μm至 75 μm，並搭配多模光纖做最後的收光，其模擬結果的光耦合效率從52.4%(35μm)到36.8%(75μm)。再來，當我們確認光源的準直誤差容忍度，首先以單模光纖作為入射光源，看光源的中心位置對應波導中心的偏移容忍度。如果我們以1dB最為分界點的時候發現，其橫向的誤差範圍約為-39 ~ 29 μm，縱向為-13.6 ~ 12.6 μm。
最後，我們在長直梯形波導中段，加上一個45度反射面擷取部分光源，達到一分為二的分光器效果，其最後光耦合效率的模擬結果，在中間擷取的光耦合效率約為8.65%(梯形頂寬35um)到27.6%(梯形頂寬75um)，而末端所收到的光耦合效率剩下48%(梯形頂寬35um)到30.3%(梯形頂寬75um)，由此我們可以發現到，在適度的結果範圍中，我們可以讓兩個接收面收到接近相同的光強，達到一分為二，且比例相同的分光效果。
最後的部分詳細列其製作的過程，從最初使用乾蝕刻畫出硬遮罩，接著以濕蝕刻製作其45度反射面，接著沉積二氧化矽（SiO2）作為絕緣層，以利未來搭配合適的IC達到整體都在同一片晶片上。製作完成之後，以光學顯微鏡與電子掃描顯微鏡(SEM)，確認其製程的結果與平整度。最後量測的結果發現，兩個接收端可以達到1比1的光強，而光學耦合效率分別是為8%。

利用矽波導與45度反射面實現1×2三維單晶片光路 1×2 3-D On-Chip Optical Path using Silicon Waveguide and 45° Reflectors ............................................................................................. i
摘要 .............................................................................................................................................. vii
Abstract ........................................................................................................................................ viii
1×2 3-D on-chip optical path using silicon waveguide and 45° reflectors...................................... 1
Chapter 1 Introduction ..................................................................................................................... 1
1-1 Background ........................................................................................................................... 1
1-2 Optical Interconnects Technologies ...................................................................................... 2
1-3 Optical Power Splitters.......................................................................................................... 6
1-4 Proposed 1×2 3-D On-Chip Optical Path using Silicon Waveguide and 45° Reflectors module ........................................................................................................................................ 9
Chapter 2 Design of 3-D on-chip optical path using Silicon Waveguide and 45° Reflectors ....... 11
2-1 Design of Straight 3-D On-Chip Optical Path .................................................................... 13
2-1-1 Coupling Efficiency between Straight 3-D Waveguide Outputs and MMF ................ 14
2-1-2 Alignment Tolerance between Straight 3-D Waveguide Input port and SMF ............ 15
2-2 Design of 1×2 3-D on-chip Optical Path ............................................................................. 16
2-2-1 Coupling Efficiency between Splitter 3-D Waveguide Outputs and MMF ................. 17
Chapter 3 Fabrication of 3-D on-chip Optical Path using Silicon Waveguide and 45° Reflectors 19
3-1 Fabrication Process of Trapezoidal Silicon Waveguide with 45° Reflectors ..................... 19
3-2 Polishing of Trapezoidal Silicon Waveguide Substrate ...................................................... 22
Chapter 4 Optical Characteristics of 1×2 3-D On-Chip Optical Path using Silicon Waveguide and 45° Reflectors ............................................................................................................................... 24
4-1 Measurement Setup ................................................................................................................. 24
4-2 Coupling Efficiency Measurement Setup ............................................................................... 25
4-3 Alignment Tolerance Measurement Setup .............................................................................. 26
Chapter 5 Summary ....................................................................................................................... 30
References .................................................................................................................................... 32

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