臺灣博碩士論文加值系統

隨著積體電路技術之精進，現今的電路功能日趨複雜。為了滿足大量製造之需求，自動測試成為積體電路製造過程中非常重要的一環。其中，自動測試儀器被廣泛運用，其前端模組核心電路之一即為數位至時間轉換器(Digital-to-Time Converter，簡稱DTC)。
本論文提出以兩組鎖相迴路(Phase-Locked Loop，簡稱PLL)為核心，取代延遲矩陣來實現數位至時間轉換器，並透過雙倍資料率技術提高可用之相位數，以提高精度並大幅縮減所需之面積與成本。
本電路以Altera Stratix IV EP4SGX230KF40C2N晶片來實現，主PLLM頻率為50 MHz，分做5組輸出相位，次PLLn超頻32倍達1600 MHz，分做4組輸出相位，最終共可提供有效40組輸出相位，有效解析度達 15.6 ps。

With the technology evolution, chips become much more complicated than ever. For mass production, automatic test equipement (ATE) plays a dominating in semiconductor fabrication. Meanwhile, the digital-to-time converter (DTC) is the key building block in ATE front-end circuit. The thesis focuses on the design of DTC.
Instead of traditional delay matrix, a dual phase-locked loops (PLLs) capable of double date rate (DDR) operation is proposed to be the TDC timing core for accuracy enhancement and cost area reduction.
The TDC is implemented with Altera Stratix IV EP4SGX230KF40C2N chip. The primary PLL operates at 50 MHz with 5 output phases. The secondary PLLs are overclocked by 32 times to operate at 1600 MHz and each posseses 4 output phases. There are overall 40 phases of the final PLL timing matrix realized and the effective LSB width is 15.6 ps.

中文摘要 I
Abstract II
誌 謝 III
目 錄 IV
圖目錄 VI
表目錄 IX
第一章 序論 1
1.1 研究動機 1
1.2 章節編排方式 2
第二章 數位至時間轉換器 3
2.1 數位至時間轉換器簡介 3
2.2 絕對時間延遲之數位至時間轉換器 5
2.3 相對時間延遲之數位至時間轉換器 8
第三章 以雙鎖相迴路與雙倍資料率實現之 FPGA數位至時間轉換器原理與設計 17
3.1 內嵌於FPGA晶片內的鎖相迴路簡介 17
3.2 電路實現過程與改良 19
3.2.1 架構起源 19
3.2.2 超頻比O之設計原理 21
3.2.3 雙倍資料傳輸率 27
3.3.4 本論文之電路架構 32
第四章 FPGA開發板介紹 34
4.1 FPGA開發平台簡介 34
4.2 本論文所使用之FPGA開發平台 35
第五章 數位至時間轉換器之模擬與驗證 39
5.1 鎖相迴路之模擬 39
5.2 輸出脈衝產生器之模擬 40
5.3 整體電路之模擬 43
第六章 量測結果與未來展望 44
6.1 量測儀器簡介 45
6.2 量測環境的建立 48
6.3 測量結果 49
6.4 結論與未來展望 51
參考文獻 52

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