臺灣博碩士論文加值系統

近年來由於無線通信的技術大量的應用於諸如GSM、GPRS、Bluetooth、WLAN (wireless local-area network)。由於網際網路的發展造成WLAN成為重要的解決方案，造就另一個商機的興起，使其逐漸成為生活中部不可或缺的一部份。
本論文電路主要為降頻轉換混波器使用雙平衡式的混波器(double balance Gilbert cell mixer)屬於主動混波器的形式，可提供轉換增益及有效消除偶次項的諧波且加強本地振盪埠(LO port)至射頻埠(RF port)的隔絕度(isolation)。此外，混波器前級接上一低雜訊放大器，其低雜訊放大器內包含帶拒濾波器(notch filter)的架構是為取代鏡像濾波器(image reject filter)，形成超外差(super heterodyne)架構的前端接收機。
所設計混波器之射頻(RF)為2.44GHz、本地振盪頻率(LO)為2.04GHz、中頻(IF)為400MHz。混波器所使用之電壓供應為1.8V，功率消耗為38mW，轉換增益(conversion gain)為5.1dB，雜訊指數(noise figure)為4.7dB，輸入三階交叉點(IIP3)為-5dBm，以及1dB壓縮點( )為-14.2dBm。混波器的埠與埠隔絕(port-to-port isolation)皆大於30dB，而接收機前端的轉換增益(conversion gain)為21.1dB，雜訊指數(noise figure)為2.8dB。
本論文中所設計之前端接收機電路由採用TSMC 0.18um製程，晶片面積為0.95´0.98 mm2。

Recently, the technologies of wireless communication are applied extensively to such as GSM, GPRS, Bluetooth, and WLAN. Therefore, WLAN becomes an important solution to the development of internet, and then has gradually become essential to life and create another rise for the opportunity of commerce.
The main purpose of this thesis is to adopt the double balance Gilbert cell mixer, proving better conversion gain, even order harmonics elimination and isolation enhancement of LO port to RF port. Furthermore, a low noise amplifier incorporating a notch filter is a promising method for cost reduction since the traditional image reject filter is not used in the receiving path. As previous method, a mixer and a low noise amplifier incorporating a notch filter constitute the receiver front-end circuit of super heterodyne architecture.
The proposed double balance Gilbert cell mixer is fabricated with TSMC CMOS 0.18um 1P6M process. While RF is set to 2.44GHz, LO 2.04GHz, and IF 400MHz, the simulation results show 5.1dB conversion gain, 4.7dB noise figure, -5dBm IIP3, and -14.2 dBm P-1dB in the 400MHz band. The supply voltage of proposed mixer is 1.8V with the total power consumption of 38mW. In addition, the simulation results of receiver front-end circuit show 21.1dB conversion gain and 2.8dB noise figure.
The chip area occupied by proposed the receiver front-end circuit is 0.95´0.98 mm2.

Contents
Abstract (Chinese) i
Abstract (English) ii
誌謝 iii
Content iv
List of Tables vi
List of Figures vii
CHAPTER 1 INTRODUCTION 01
1.1 Background and Motivation 01
1.2 Thesis Organization 02
CHAPTER 2 CONSIDERATION OF SYSTEM DESIGN 03
2.1 TSMC Device Model 03
2.1.1 Inductor 03
2.1.2 Capacitor 04
2.1.3 Resistor 05
2.1.4 MOS 06
2.1.5 IC Design Flow 10
2.2 General Consideration in Mixer and LNA 12
2.2.1 Gain and Stability 12
2.2.2 Noise 17
2.2.3 Linearity 21
2.2.4 Port to Port Isolation 24
2.3 IEEE 802.11b Receiver Specifications 27
CHAPTER 3 REVIEW OF RECEIVER ARCHITECHTURES 30
3.1 Receiver Architectures 30
3.1.1 Super Heterodyne Architecture 31
3.1.2 Homodyne Architecture 32
3.1.3 Image Reject Architecture 36
3.2 Mixer Topology 40
3.2.1 Passive Mixer 40
3.2.2 Active Mixer 44
3.3 LNA Topology 47
3.3.1 Cascode LNA 47
3.3.2 Differential LNA 48
CHAPTER 4 DESIGN OF A 2.4GHZ RECEIVER 49
4.1 Mixer Design Flow 49
4.2 Theory of CMOS Gilbert-Cell Operation 51
4.3 Mixer Simulation Result 56
4.4 Receiver Circuit and Simulation Result 64
4.5 Layout of Receiver Front-End Circuit 69
CHAPTER 5 CONCLUSION 70
REFERENCE 71

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