臺灣博碩士論文加值系統

錯誤更正碼和內建自我修復為兩種廣泛用來提升記憶體良率和可靠度的方法，過去已有不同種類的內建備份記憶體分析演算法和錯誤更正碼被提出，但這些方法都著重在單一修復方法的運用上。在這篇論文中，我們提出了一個結合錯誤更正碼和內建自我修復的方法用來提升記憶體的良率。在先進的記憶體裡，大部分的記憶體都包含了錯誤更正碼和內建自我修復的架構，我們利用不同的修復順序使備份記憶體的使用效率提升，並進而讓整體記憶體的良率提升。
首先，我們使用十萬個4Mb的商用記憶體來分析不同類型錯誤的分布情形，並根據分析的結果初步的分析我們提出方法的使用效率，再來，利用這些記憶體的錯誤位元資訊實際模擬我們所提出的方法。從實驗結果可以發現，我們所提出來的方法相較於傳統結合錯誤更正碼和內建自我修復方法，在記憶體良率方面可提高2%以上。我們也分析不同的錯誤更正碼結合內建自我修復架構的可靠度，從實驗結果可得知，我們所提出的方法並不會造成記憶體的可靠度損失太多。在這篇論文中，我們針對不同產品的記憶體所要求的良率及可靠度做分析，利用所提出的修復方法結合不同的錯誤更正碼和內建自我修復的架構以達到目標。

Error correction code (ECC) and built-in self-repair (BISR) schemes have been wildly used for improving the yield and reliability of memories. Many built-in redundancy-analysis (BIRA) algorithms and ECC schemes have been reported before. However, most of them focus on either BIRA algorithms or ECC schemes. In this thesis, we propose an ECC-Enhanced Memory Repair (EEMR) scheme for yield improvement. Many modern memories are equipped with ECC in addition to BISR. We evaluate the back-end flow that combines both ECC and BIRA to determine whether yield can be improved by proper sequencing of the two steps. We also collect and identify important failure patterns and their distributions from over 100,000 sample memory instances, which are used to enhance the EEMR scheme that incorporates ECC. As ECC is failure pattern sensitive, careful evaluation from realistic failure bitmaps is necessary. We also verify the feasibility of implementing the proposed EEMR scheme by real test data. Experimental results from industrial 4Mb memory instances show that the proposed EEMR scheme gains over 2% instance yield on average, as compared with the traditional scheme. We also investigate the reliability of the EEMR scheme with different ECC specifications and BIRA algorithms.

Abstract
List of Figures
List of Tables
CHAPTER 1 INTRODUCTION
1.1 Motivation
1.2 The Different Memory Repair Schemes
1.3 The proposed scheme
1.4 Thesis Organization
CHAPTER 2 Background
2.1 Built-In Self-Test (BIST), Built-In Self-Repair (BISR), and Built-In Redundancy-Analysis (BIRA) Algorithms
2.2 Error Correction Codes
2.3 The Traditional Scheme Combining the Repair Redundancy and ECC
2.4 Reliability and Mean Time to Failure (MTTF)
CHAPTER 3 Proposed ECC-Enhanced Memory Repair (EEMR) Scheme for Yield Improvement
3.1 Failure Pattern Distribution
3.2 Failure Escape
3.3 The Proposed EEMR Scheme
3.4 Proposed ECC-Enhanced BIRA Algorithms
CHAPTER 4 EXPERIMENTAL RESULTS
4.1 Preliminaries
4.2 Instance Yield Statistics
4.3 Defect Level Analysis
4.4 RA Only Scheme vs. Proposed Scheme
4.5 Reliability Emulation
CHAPTER 5 CONCLUSIONS AND FUTURE WORK
5.1 Conclusions
5.2 Future Work
Bibliography

[1] Semiconductor Industry Association. (International Technology Roadmap for Semiconductors (ITRS), 2009 Edition.
[2] L.-T. Wang, C.-W. Wu, and X. Wen, Design for Testability: VLSI Test Principles and Architectures. San Francisco: Elsevier (Morgan Kaufmann), 2006.
[3] S. Hamdioui, G. Gaydadjiev, Ad J. van de Goor, “The state-of-art and future trends in testing embedded memories,“ IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2004, pp. 54–59.
[4] N. Derhacobian, V. A. Vardanian, and Y. Zorian, “Embedded memory reliability: The SER challenge”, IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2004, pp. 104–110.
[5] Xiaogang Du, S. M. Reddy, Wu-Tung Cheng, J. Rayhawk, and N. Mukherjee, "At-speed Built-in Self-repair Analyzer for Embedded Word-oriented Memories," IEEE Int. Conf. on VLSI Design, 2004, pp. 895-900.
[6] H.-N. Liu, Y.-J. Huang, J.-F. Li, “Memory Built-in Self-Test in Multicore Chips with Mesh-Based Networks,” IEEE Micro, vol. 29, Sept.-Oct. 2009, pp. 46-55.
[7] L.-M. Denq, Y.-T. Hsing, C.-W. Wu, “Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories,” IEEE Design &; Test of Computers, vol. 26, Mar.-Apr. 2009, pp. 64-73.
[8] M. Nicolaidis, N. Achouri, S. Boutobza, "Optimal reconfiguration functions for column or data-bit built-in self-repair," Proc. of the Design, Automation and Test in Europe Conference and Exhibition (DATE), 2003, pp. 590-595.
[9] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, "Built-In Redundancy Analysis for Memory Yield Improvement", IEEE Trans. on Reliability (TR), vol. 52, Dec. 2003, pp. 386-399.
[10] S.-K. Lu, Y.-C. Tsai, C.-H. Hsu, K.-H. Wang, and C.-W. Wu, "Efficient Built-In Redundancy Analysis for Embedded Memories with 2-D Redundancy," IEEE Trans. on VLSI Systems, vol. 14, Jan. 2006, pp. 34-42.
[11] Yu-Jen Huang, Da-Ming Chang, and Jin-Fu Li, "A Built-In Redundancy-Analysis Scheme for Self-Reparable RAMs with Two-Level Redundancy," IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Oct. 2006, pp. 362-370.
[12] Joohwan Lee, Kihyun Park, and Sungho Kang, "An Area-efficient Built-in Redundancy Analysis for Embedded Memories with Optimal Repair Rate Using 2-D Redundancy," in International SOC Design Conference (ISOCC), Nov. 2009, pp. 353-356.
[13] Mincent Lee, L.-M. Denq, and C.-W. Wu, “A Memory Built-In Self-Repair Scheme Based on Configurable Spares”,IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 30, Jun. 2011, pp. 919-929.
[14] Zaid Al-Ars, and Ad J. van de Goor, "Soft faults and importance of stresses in memory testing", Proc. of the Design, Automation and Test in Europe Conference and Exhibition (DATE), Feb. 2004, pp. 1084-1089.
[15] D. Rossi, N. Timoncini, M. Spica, and C. Metra, “Error correcting code analysis for cache memory high reliability and performance,” Proc. of the Design, Automation and Test in Europe Conference and Exhibition (DATE), 2011, pp. 1-6.
[16] D.-C. Bossen, M.-Y. Hsiao, "A System Solution to the Memory Soft Error Problem", IBM Journal of Research and Development, May 1980, pp. 390-397.
[17] Po-Yuan Chen et al., "An Enhanced EDAC Methodology for Low Power PSRAM", IEEE International Test Conference (ITC), Oct. 2006, pp. 1-10.
[18] G. C. Cardarilli, S. Pontarelli, M. Re, and A. Salsano, "Analysis of Errors and Erasures in Parity Sharing RS Codecs", IEEE Trans. on Computers (TC), vol. 56, Dec. 2007, pp. 1721-1726.
[19] Shu Lin and Daniel J. Costello, Error control coding: fundamentals and applications, Prentice-Hall, 2nd Edition, 2004.
[20] C.-H. Stapper and H.-S. Lee, “Synergistic Fault-Tolerance for Memory Chips”, IEEE Trans. On Computers (TC), vol. 41, Sep. 1992, pp. 1078-1087.
[21] Yun-Sang Lee, Jung-Bae Lee, Chang-Hyun Kim, Sang-Uhn Cha, and Hongil Yoon, " An Efficient Self Post Package Repair Algorithm and Implementation in Memory System with on-chip-ECC", IEEE Asian Solid-State Circuit Conference (ASSCC), Nov. 2006, pp. 331-334.
[22] C.-H. Stapper, J.-A. Fifield, H.-L. Kalter, and W.-A. Klassen, “High-Reliability Fault-Tolerance 16-MBit Memory Chips”, IEEE Trans. On Reliability (TR), vol. 42, Dec. 1993, pp. 596-603.
[23] C.M. Jeffery, A. Basagalar, R.J.O. Figueiredo, "Dynamic sparing and error correction techniques for fault tolerance in nanoscale memory structures", IEEE Conference on Nanotechnology (NANO), Aug. 2004, pp. 168-170.
[24] M. Nicolaidis, N. Achouri, and L. Anghel, "A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies", VLSI Test Symposium (VTS), April 2004, pp. 313-318.
[25] C.-L. Su, Y.-T. Yeh, and C.-W. Wu, "An integrated ECC and redundancy repair scheme for memory reliability enhancement", Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Oct. 2005, pp. 81-89.
[26] R. C. Baumann, “Soft errors in advanced semiconductor devices—Part I: The three radiation sources”, IEEE Trans. Device and Materials Reliability, vol. 1, no. 1, pp. 17–22, Mar. 2001.
[27] R. W. Hamming, “Error Detecting and Error Correcting Codes”, Bell System Tech. J., vol. XXVI, pp. 147-160, Apr. 1950.
[28] J. L. Massey, “Shift-register Synthesis and BCH Decoding”, IEEE Trans. on Information Theory, vol. 15, pp. 122-127, 1969.
[29] R. Chien, “Cyclic Decoding Procedures for Bose-Chaudhuri-Hocquenghem Codes”, IEEE Trans. on Information Theory, vol. 10, pp. 357-363, 1964.
[30] C. R. Knight, E. R. Jervis, and G. R. Herd, “The Definition of Terms of Interest in the Study of Reliability”, IRE Trans. On Reliability and Quality Control, vol. PGRQC-5, pp34-56, April 1955.
[31] B.-Y. Lin, M. Lee, and C.-W. Wu, “MFA: A Memory-Failure Analyzer for Memory Diagnosis and Repair”, in Proc. IEEE VLSI Test Symposium (VTS), April 2012.
[32] D. Rossi, N. Timoncini, M. Spica and C. Metra, “Error Correcting Code Analysis for Cache Memory High Reliability and Performance”, Proc. of the Design, Automation and Test in Europe Conference and Exhibition (DATE), 2011, pp. 1-6.