臺灣博碩士論文加值系統

在本篇論文中，我們設計了一個合成器來合成各種組合電路，建立以開關電晶體為主的電路，輸入為布林函數的格式，可以同時輸入數個函數讓硬體共享，針對不同的電路特性利用RC delay model做最佳化，節省面積與提高速度，最後輸出為Verilog gate-level code與HSPICE netlist，以提供Verilog-in和模擬使用。最佳化所需的執行時間短，可快速的得到最好的結果。

In this thesis, An automatic optimization logic synthesizer in pass-transistor-based is developed for logic mapping of the combinational circuits. The format of inputs is Boolean functions with expression of sum of product and we can input several functions for hardware sharing at the same time. Depending the difference of circuits, we use the RC delay model to do optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. It only needs little executing time for searching the best result and we can quickly gate it.

第1章 導論 1
1.1 論文架構 1
1.2 動機說明 1
第2章 電路 4
2.1 簡介 4
2.2 CMOS電路 4
2.3 CPL電路 5
2.4 SRPL電路 6
2.5 DCVSPG電路 7
2.6 EEPL電路 8
2.7 DPL電路 9
2.8 LEAP電路 10
2.9 電路分析與比較 11
第3章 邏輯合成器 17
3.1 簡介 17
3.2 BDD TREE化簡 18
3.3 加入反相器 22
3.3.1 不同層級加入P-latch inverter的影響 23
3.3.2 P-latch inverter 24
3.4 邏輯合成器流程圖 29
第4章 最佳化 30
4.1 簡介 30
4.2 RC DELAY MODEL 30
4.3 電晶體寬度選擇 31
4.3.1 方法一 32
4.3.2 方法二 33
4.3.3 方法三 34
4.3.4 比較 36
4.4 順序選擇 37
第5章 結果比較 40
5.1 簡介 40
5.2 HSPICE 最佳化結果比較 40
5.2.1 C4 40
5.2.2 C8 41
5.2.3 C16 42
5.3 討論 42
第6章 結論與未來工作 44
6.1 結論 44
6.2 未來工作 44
第7章 參考文獻 45

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